Rasit Onur Topaloglu  Rasit Onur Topaloglu photo       

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Advisory R&D Engineer / Technical Lead

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Professional Associations

Professional Associations:  ACM  |  IEEE   |  IEEE Council on EDA  |  IEEE Mid-Hudson Section  |  SPIE -- International Society of Optical Engineering


2017

Mask decomposition and optimization for directed self assembly
Lai, Kafai and Topaloglu, Rasit O
US Patent 9,569,578
Abstract


2016

Stacked carbon nanotube multiple threshold device
Rosenblatt, Sami and Topaloglu, Rasit Onur
US Patent 9,472,773
Abstract

DIVIDING LITHOGRAPHY EXPOSURE FIELDS TO IMPROVE SEMICONDUCTOR FABRICATION
Greco, Stephen E and Topaloglu, Rasit O
US Patent 20,160,180,003

MULTIPLE-DEPTH TRENCH INTERCONNECT TECHNOLOGY AT ADVANCED SEMICONDUCTOR NODES
Greco, Stephen E and Mcgahay, Vincent J and Topaloglu, Rasit O
US Patent 20,160,042,114


2015

Dynamic intrinsic chip identification
Kothandaraman, Chandrasekharan and Rosenblatt, Sami and TOPALOGLU, Rasit O
US Patent App. 14/975,512
Abstract

Reliability of an electronic device
Liebmann, Lars W and Topaloglu, Rasit O
US Patent App. 14/838,705
Abstract

Integrated circuit systems including vertical inductors
Topaloglu, Rasit O
US Patent 9,159,711

Interconnect level structures for confining stitch-induced via structures
Greco, Stephen E and Topaloglu, Rasit O
US Patent App. 14/873,824

Reticle data decomposition for focal plane determination in lithographic processes
Greco, Stephen E and Stobert, Ian P and Topaloglu, Rasit O
US Patent 9,058,457

Early overlay prediction and overlay-aware mask design
Greco, Stephen E and TOPALOGLU, Rasit O
US Patent App. 14/753,344
Abstract


2014

Stitch-derived via structures and methods of generating the same
Greco, Stephen E and McGahay, Vincent J and Topaloglu, Rasit O
US Patent App. 14/285,719



2013

Interconnect level structures for confining stitch-induced via structures
Greco, Stephen E and Topaloglu, Rasit O
US Patent App. 13/849,796


2012


Two-step simulation methodology for aging simulations
Topaloglu, Rasit O and Goo, Jung-Suk
US Patent 8,099,269






2011




2010

Double layer stress for multiple gate transistors
Topaloglu, Rasit O
US Patent 7,671,418



2009