Robert K. (Bob) Montoye  Robert K. (Bob) Montoye photo       

contact information

RSM
Thomas J. Watson Research Center, Yorktown Heights, NY USA
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Professional Associations

Professional Associations:  ACM  |  IEEE


2014

1 Mb 0.41 $mu$m$^2$ 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing
Li, Jing and Montoye, Robert K and Ishii, Masatoshi and Chang, Leland
IEEE Journal of Solid-State Circuits 49(4), 896--907, IEEE, 2014
Abstract

Matrix-matrix multiplication on a large register file architecture with indirection
Sreedhar, Dheeraj and Derby, Jeff H and Montoye, Robert K and Johnson, CL
High Performance Computing (HiPC), 2014 21st International Conference on, pp. 1--10
Abstract

1 Mb 0.41 $mu$m$^2$ 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing
Li, Jing and Montoye, Robert K and Ishii, Masatoshi and Chang, Leland
IEEE Journal of Solid-State Circuits 49(4), 896--907, IEEE, 2014
Abstract


2013

Processor architecture for software implementation of multi-sector G-RAKE receivers for HSUPA wireless infrastructure
Sreedhar, Dheeraj and Derby, Jeff H and Vega, AJ and Rogers, B and Johnson, CL and Montoye, Robert K
Acoustics, Speech and Signal Processing (ICASSP), 2013 IEEE International Conference on, pp. 2770--2774
Abstract

A 0.1 pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI
Liu, Yong and Hsieh, Ping-Hsuan and Kim, Seongwon and Seo, Jae-sun and Montoye, Robert and Chang, Leland and Tierno, Jose and Friedman, Daniel
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International, pp. 400--401
Abstract


2012

Deep trench capacitors for switched-capacitor voltage converters
Seo, Jae-sun and Young, Albert and Montoye, Robert and Chang, Leland
Int. Workshop on Power Supply on Chip, 2012
Abstract

Architectural perspectives of future wireless base stations based on the IBM PowerEN™ processor
Vega, Augusto and Bose, Pradip and Buyuktosunoglu, Alper and Derby, Jeff and Franceschini, Michele and Johnson, Charles and Montoye, Robert
High Performance Computer Architecture (HPCA), 2012 IEEE 18th International Symposium on, pp. 1--10
Abstract


2011

Demonstration of CAM and TCAM using phase change devices
Rajendran, Bipin and Cheek, Roger W and Lastras, Luis A and Franceschini, Michele M and Breitwisch, Matthew J and Schrott, Alejandro G and Li, Jing and Montoye, Robert K and Chang, Leland and Lam, Chung
Memory Workshop (IMW), 2011 3rd IEEE International, pp. 1--4
Abstract


2010

A fully-integrated switched-capacitor 2∶ 1 voltage converter with regulation capability and 90\% efficiency at 2.3 A/mm 2
Chang, Leland and Montoye, Robert K and Ji, Brian L and Weger, Alan J and Stawiasz, Kevin G and Dennard, Robert H
VLSI Circuits (VLSIC), 2010 IEEE Symposium on, pp. 55--56
Abstract

Practical strategies for power-efficient computing technologies
Chang, Leland and Frank, David J and Montoye, Robert K and Koester, Steven J and Ji, Brian L and Coteus, Paul W and Dennard, Robert H and Haensch, Wilfried
Proceedings of the IEEE 98(2), 215--236, IEEE, 2010
Abstract

Performance and power evaluation of an in-line accelerator
Rico, Alejandro and Derby, Jeff H and Montoye, Robert K and Heil, Timothy H and Cher, Chen-Yong and Bose, Pradip
Proceedings of the 7th ACM international conference on Computing frontiers, pp. 81--82, 2010
Abstract

A 270ps 20mW 108-bit end-around carry adder for multiply-add fused floating point unit
Zhang, Xiao Yan and Chan, Yiu-Hing and Montoye, Robert and Sigal, Leon and Schwarz, Eric and Kelly, Michael
Journal of Signal Processing Systems 58(2), 139--144, Springer, 2010
Abstract

A fully-integrated switched-capacitor 2∶ 1 voltage converter with regulation capability and 90\% efficiency at 2.3 A/mm 2
Chang, Leland and Montoye, Robert K and Ji, Brian L and Weger, Alan J and Stawiasz, Kevin G and Dennard, Robert H
VLSI Circuits (VLSIC), 2010 IEEE Symposium on, pp. 55--56
Abstract


2008

Custom is from Venus and synthesis from Mars
Puri, Ruchir and Joyner, William H and Borkar, Shekhar and Garibay, Ty and Lotz, Jonathan and Montoye, Robert
Proceedings of the 45th annual Design Automation Conference, pp. 992--992, 2008
Abstract

An 8T-SRAM for variability tolerance and low-voltage operation in high-performance caches
Chang, Leland and Montoye, Robert K and Nakamura, Yutaka and Batson, Kevin A and Eickemeyer, Richard J and Dennard, Robert H and Haensch, Wilfried and Jamsek, Damir
IEEE Journal of Solid-State Circuits 43(4), 956--963, IEEE, 2008
Abstract


2007

A 5.3 GHz 8T-SRAM with operation down to 0.41 V in 65nm CMOS
Chang, Leland and Nakamura, Yutaka and Montoye, Robert K and Sawada, Jun and Martin, Andrew K and Kinoshita, Kiyofumi and Gebara, Fadi H and Agarwal, Kanak B and Acharyya, Dhruva J and Haensch, Wilfried and others
VLSI Circuits, 2007 IEEE Symposium on, pp. 252--253
Abstract


2006

Circuit design style for energy efficiency: LSDL and compound domino
Yu, Xiao Yan and Montoye, Robert and Nowka, Kevin and Zeydel, Bart and Oklobdzija, Vojin
International Workshop on Power and Timing Modeling, Optimization and Simulation, pp. 47--55, 2006
Abstract

A duty-cycle correction circuit for high-frequency clocks
Agarwal, Kanak and Montoye, Robert
VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on, pp. 106--107
Abstract

VICTORIA: VMX indirect compute technology oriented towards in-line acceleration
Derby, Jeff H and Montoye, Robert K and Moreira, Jos{'e}
Proceedings of the 3rd conference on Computing frontiers, pp. 303--312, 2006
Abstract

Limited switch dynamic logic circuits for high-speed low-power circuit design
Belluomini, Wendy and Jamsek, Damir and Martin, Andrew K and McDowell, Chandler and Montoye, Robert K and Ngo, Hung C and Sawada, Jun
IBM journal of research and development 50(2.3), 277--286, IBM, 2006
Abstract


2005

Controlled-load limited switch dynamic logic circuit
Sivagnaname, Jayakumaran and Ngo, Hung C and Nowka, Kevin J and Montoye, Robert K and Brown, Richard B
Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on, pp. 83--87
Abstract

An 8GHz floating-point multiply
Belluomini, WENDY and Jamsek, DAMIR and Martin, Andrew and McDowell, Chandler and Montoye, Robert and Nguyen, Tuyet and Ngo, Hung and Sawada, Jun and Vo, Ivan and Datta, Ramyanshu
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International, pp. 374--604
Abstract

Testing and debugging delay faults in dynamic circuits
Datta, Ramyanshu and Nassif, Sani and Montoye, Robert and Abraham, Jacob A
Test Conference, 2005. Proceedings. ITC 2005. IEEE International, pp. 10--pp
Abstract

Stable SRAM cell design for the 32 nm node and beyond
Chang, Leland and Fried, David M and Hergenrother, Jack and Sleight, Jeffrey W and Dennard, Robert H and Montoye, Robert K and Sekaric, Lidija and McNab, Sharee J and Topol, Anna W and Adams, Charlotte D and others
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on, pp. 128--129
Abstract


2003

Value-based management of design reuse
Carballo, Juan Antonio and Cohn, David L and Belluomini, Wendy and Montoye, Robert K
Advanced Microelectronic Manufacturing, pp. 72--81, 2003
Abstract

A double precision floating point multiply
Montoye, Robert and Belluomini, Wendy and Ngo, Hung and McDowell, Chandler and Sawada, Jun and Nguyen, Tuyet and Veraa, Brian and Wagoner, James and Lee, Mike
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International, pp. 336--337
Abstract


2000

Ratioed CMOS: A low power high speed design choice in SOI technologies
Tretz, Christophe R and Montoye, Robert K and Reohr, William
SOI Conference, 2000 IEEE International, pp. 28--29
Abstract


1998

A decompression core for PowerPC
Kemp, Timothy M and Montoye, Robert K and Harper, Jeffrey D and Palmer, John D and Auerbach, Daniel J
IBM Journal of Research and Development 42(6), 807--812, IBM, 1998
Abstract


1990

Data cache and storage control units
Hardell, William R and Hicks, Dwain A and Howell, Lawrence C and Maule, Warren E and Montoye, Robert and Tuttle, David P
iBM RISC System/6000 Technology, 44--50, 1990

Data cache and storage control units
Hardell, William R and Hicks, Dwain A and Howell, Lawrence C and Maule, Warren E and Montoye, Robert and Tuttle, David P
iBM RISC System/6000 Technology, 44--50, 1990

RISC System/6000 floating-point unit
Olsson, Brett and Montoye, Robert and Markstein, Peter and NguyenPhu, M
IBM RISC System/6000 Technology, 34--43, International Business Machines Corporation, Order No. SA23-2619, 1990

Second-generation RISC floating point with multiply-add fused
Hokenek, Erdem and Montoye, Robert K and Cook, Peter W
IEEE Journal of Solid-State Circuits 25(5), 1207--1213, IEEE, 1990
Abstract

The IBM RISC System/6000 processor: hardware overview
Bakoglu, HB and Grohoski, Gregory F. and Montoye, Robert K.
IBM Journal of Research and Development 34(1), 12--22, IBM, 1990
Abstract

Leading-zero anticipator (LZA) in the IBM RISC System/6000 floating-point execution unit
Hokenek, Erdem and Montoye, Robert K.
IBM Journal of Research and Development 34(1), 71--77, IBM, 1990
Abstract

Design of the IBM RISC System/6000 floating-point execution unit
Montoye, Robert K. and Hokenek, Erdem and Runyon, Stephen L.
IBM Journal of research and development 34(1), 59--70, IBM, 1990
Abstract


1986

Design-performance trade-offs in CMOS-domino logic
Oklobdzija, Vojin G and Montoye, Robert Kevin
IEEE journal of solid-state circuits 21(2), 304--306, IEEE, 1986
Abstract


1982

A Practical Algorithm for the Solution of
Montoye, Robert K and Lawrie, Duncan H
IEEE Transactions on Computers 100(31), 1982
Abstract


1981

Area-time efficient addition in charge based technology
Montoye, Robert K
Proceedings of the 18th Design Automation Conference, pp. 862--872, 1981
Abstract


Year Unknown

ISSCC 2003/SESSION 19/PROCESSOR BUILDING BLOCKS/PAPER 19.2
Montoye, Robert and Belluomini, Wendy and Ngo, Hung and McDowell, Chandler and Sawada, Jun and Nguyen, Tuyet and Veraa, Brian and Wagoner, James and Lee, Mike
R Montoye, W Belluomini, H Ngo, C McDowell…, 0

ISSCC 2003/SESSION 19/PROCESSOR BUILDING BLOCKS/PAPER 19.2
Montoye, Robert and Belluomini, Wendy and Ngo, Hung and McDowell, Chandler and Sawada, Jun and Nguyen, Tuyet and Veraa, Brian and Wagoner, James and Lee, Mike
R Montoye, W Belluomini, H Ngo, C McDowell…, 0

ISSCC 2003/SESSION 19/PROCESSOR BUILDING BLOCKS/PAPER 19.2
Montoye, Robert and Belluomini, Wendy and Ngo, Hung and McDowell, Chandler and Sawada, Jun and Nguyen, Tuyet and Veraa, Brian and Wagoner, James and Lee, Mike
R Montoye, W Belluomini, H Ngo, C McDowell…, 0

ISSCC 2003/SESSION 19/PROCESSOR BUILDING BLOCKS/PAPER 19.2
Montoye, Robert and Belluomini, Wendy and Ngo, Hung and McDowell, Chandler and Sawada, Jun and Nguyen, Tuyet and Veraa, Brian and Wagoner, James and Lee, Mike
R Montoye, W Belluomini, H Ngo, C McDowell…, 0