Katsuyuki Sakuma  Katsuyuki Sakuma photo       

contact information

Research Staff Member
Thomas J. Watson Research Center, Yorktown Heights, NY USA
  +1dash914dash945dash2080

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Professional Associations

Professional Associations:  IEEE Components, Packaging and Manufacturing Technology Society  |  IEEE, Senior Member


2017

Reduced volume interconnect for three-dimensional chip stack
Peter Gruber, Katsuyuki Sakuma, D-Y Shih
US Patent 9,679,875B2

Flexible electronics for wearable healthcare sensors
Huan Hu, Ning Li, Xiao Hu Liu, Katsuyuki Sakuma
US patent, 9,670,061 B1

Visualization of alignment marks on a chip covered by a pre-applied underfill
Katsuyuki Sakuma, Mukta G. Farooq, Jae-Woong Nah
US patent, 9,633,925

Method for establishing interconnects in packages using thin interposers
Benjamin Fasano, Michael Cranmer, Richard Indyk, Harry Cox, Katsuyuki Sakuma, Eric Perfecto
US patent, 9,607,973



2016

Flip chip alignment mark exposing method enabling wafer level underfill
M. Farooq, K. Petrarca, N. Polomoff, K. Sakuma
US patent application, US2016/0365281A1

Formation of through-silicon via (TSV) in silicon substrate
Katsuyuki Sakuma
JP Patent 6021125

Selective area heating for 3D chip stack
Mario Interrante, Katsuyuki Sakuma
Chinese Patent, ZL20140081598.1

Selective area heating for 3D chip stack
Mario Interrante, Katsuyuki Sakuma
US Patent 9,431,366


Ball grid array and land grid array assemblies fabricated using temporary resist
Nah, Jae-Woong and Reynolds, Charles L and Sakuma, Katsuyuki
US Patent 9,263,378

FLIP-CHIP BONDER WITH INDUCTION COILS
Nah, Jae-woong and Quesnel, S{'e}bastien S and Sakuma, Katsuyuki
US Patent application 2016/0141264

Integrated circuit bonding with interposer die
Interrante, Mario J and Sakuma, Katsuyuki
US Patent 9,373,590 B1

Method and structure of die stacking using pre-applied underfill
Farooq, Mukta G and Gaynes, Michael A and Sakuma, Katsuyuki
US Patent 9,330,946


2015

3D bond and assembly process for severely bowed interposer die
Interrante, Marcus E and Interrante, Mario J and Sakuma, Katsuyuki
US Patent 9,224,712

METHOD FOR FORMING STUDS USED FOR SELF-ALIGNMENT OF SOLDER BUMPS
Katsuyuki Sakuma, Sayuri Kohara, Kuniaki Sueoka, Toriyama kazushige
Japanese Patent 5839952


Selective area heating for 3D chip stack
Mario J. Interrante, Katsuyuki Sakuma
US Patent 9105629 B2

3D assembly for interposer bow
Mario J. Interrante, Katsuyuki Sakuma
US Patent 9059241 B2




2014


Underfill material dispensing for stacked semiconductor chips
Jae-Woong Nah, Katsuyuki Sakuma, Bucknell C. Webb
US Patent 8759961 B2

Underfill material dispensing for stacked semiconductor chips
Jae-Woong Nah, Katsuyuki Sakuma, Bucknell C. Webb
US Patent 8759963 B2


2013

Advanced IMC bonding for fine pitch interconnection
K. Sakuma, K. Toriyama, and S. Kohara
Japanese Patent App. 2011-249848

Method of Stacking Silicon Chips using Cavity Template
K. Sakuma, S. Kohara, K. Sueoka, K. Toriyama
Japanese Patent App. 2011-249892

Inner Support Guide for Flip Chip and 3D Chip Stack
K. Sakuma, S. Kohara, K. Sueoka, K. Toriyama
Japanese Patent App. 2011-258013


2012



2009

Bonding Method and Bonding Equipment
S. Shoji, J. Mizuno, and K. Sakuma
Japanese Patent App. 2009-239288

Chip-to-wafer integration technology for three-dimensional chip stacking
Katsuyuki Sakuma, Paul Stephen Andry, Kuniaki Sueoka, John Ulrich Knickerbocker
US Patent 7,514,290


2006

Liquid crystal display driver and method thereof
Yoshitami Sakaguchi, Katsuyuki Sakuma, others
US Patent 7088324


2005

Liquid Crystal Display Drivers and Method Thereof
Yoshitami Sakaguchi, Katsuyuki Sakuma
Japanese Patent App. 2005-99414

Liquid crystal display
Katsuyuki Sakuma, Yoshitami Sakaguchi
US Patent 6937233 B2


2003

Liquid Crystal Display Drivers and Method Thereof
Katsuyuki Sakuma, Yoshitami Sakaguchi
Japanese Patent App.2003-15613


2002