Jeff Shearer  Jeff Shearer photo       

contact information

Interconnect Patterning
Semiconductor Technology Research, Albany, NY
  +1dash518dash292dash7468

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Professional Associations

Professional Associations:  American Vacuum Society


2017

Enabling large feature alignment marks with sidewall image transfer patterning
Cheng, Kangguo and Kanakasabapathy, Sivananda K and LIE, Fee Li and Miller, Eric R and SHEARER, Jeffrey C and Sporre, John R and TEEHAN, Sean
US Patent 9,536,744
Abstract

Method and structure for enabling controlled spacer RIE
Cheng, Kangguo and Jung, Ryan O and Lie, Fee Li and Miller, Eric R and Shearer, Jeffrey C and Sporre, John R and Teehan, Sean
US Patent 9,627,277
Abstract

Method and structure for enabling high aspect ratio sacrificial gates
Cheng, Kangguo and Jung, Ryan O and Lie, Fee Li and Shearer, Jeffrey C and Sporre, John R and Teehan, Sean
US Patent 9,659,779
Abstract


2016

Single spacer for complementary metal oxide semiconductor process flow
Bergendahl, Marc A and Cheng, Kangguo and Dechene, Jessica and Lie, Fee Li and Miller, Eric R and Shearer, Jeffrey C and Sporre, John R and Teehan, Sean
US Patent 9,450,095
Abstract