Gi-Joon Nam  Gi-Joon Nam photo       

contact information

Research Staff Member
Thomas J. Watson Research Center, Yorktown Heights, NY USA
  +1dash914dash945dash3180

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Professional Associations

Professional Associations:  ACM  |  IEEE  |  Korean-American Scientiests and Engineers Association


2014

Clock optimization with local clock buffer control optimization
Charles J Alpert, Zhuo Li, Gi-Joon Nam, David A Papa, Chin Ngai Sze, Natarajan Viswanathan
US Patent 8,667,441

Timing refinement re-routing
Michael Anthony Kazda, Zhuo Li, Gi-Joon Nam, Ying Zhou
US Patent 8,635,577

Routing centric design closure
Charles J Alpert, Zhuo Li, Gi-Joon Nam, Chin Ngai Sze, Paul G Villarrubia
US Patent 8,826,215


2013

Accuracy pin-slew mode for gate delay calculation
Charles J Alpert, Zhuo Li, Gi-Joon Nam, David A Papa, Chin Ngai Sze, Natarajan Viswanathan, Brian C Wilson
US Patent 8,418,108

Local objective optimization in global placement of an integrated circuit design
Charles J Alpert, Myung-Chul Kim, Gi-Joon Nam, Shyam Ramji, Natarajan Viswanathan
US Patent 8,595,675

Multi-patterning lithography aware cell placement in integrated circuit design
Kanak Behari Agarwal, Charles Jay Alpert, Zhuo Li, Gi-Joon Nam, Natarajan Viswanathan
US Patent 8,495,548

Latch clustering with proximity to local clock buffers
Charles Jay Alpert, Zhuo Li, Gi-Joon Nam, David Anthony Papa, Chin Ngai Sze, Natarajan Viswanathan
US Patent 8,458,634


2012

Element placement in circuit design based on preferred location
Charles J Alpert, Gi-Joon Nam, Chin Ngai Sze, Paul G Villarrubia, Natarajan Viswanathan
US Patent App. 13/485,828

Structured placement of latches/flip-flops to minimize clock power in high-performance designs
Charles J Alpert, Zhuo Li, Gi-Joon Nam, Shyam Ramji, Chin Ngai Sze, Paul G Villarrubia, Natarajan Viswanathan
US Patent App. 13/689,437

Separate refinement of local wirelength and local module density in intermediate placement of an integrated circuit design
Charles J Alpert, Myung-Chul Kim, Gi-Joon Nam, Shyam Ramji, Natarajan Viswanathan
US Patent App. 13/539,440

ELECTRONIC DESIGN AUTOMATION OBJECT PLACEMENT WITH PARTIALLY REGION-CONSTRAINED OBJECTS
C J Alpert, J L Mccann, G Nam, S Ramji, T Taghavi, N Viswanathan
US Patent 20,120,054,708


2011

Whitespace creation and preservation in circuit design
Charles Jay Alpert, Gi-Joon Nam, Shyam Ramji, Jarrod Alexander Roy, Paul G Villarrubia, Natarajan Viswanathan
US Patent App. 13/112,098

DETAILED ROUTABILITY BY CELL PLACEMENT
C J Alpert, A D Huber, Z Li, G Nam, S Ramji, J A Roy, T Taghavi, G E Tellez, P G Villarrubia, N Viswanathan, others
US Patent 20,110,302,545

POST-PLACEMENT CELL SHIFTING
C J Alpert, Z Li, G Nam, S Ramji, L N Reddy, J A Roy, T Taghavi, P G Villarrubia, N Viswanathan
US Patent 20,110,302,544


2009

Object placement in integrated circuit design
C J Alpert, G Nam, J A Roy, N Vishvanathan
US Patent App. 12/420,156

Incremental timing optimization and placement
Charles J Alpert, Zhuo Li, Gi-joon Nam, Shyam Ramji, Jarrod A Roy, Natarajan Viswanathan
US Patent App. 12/416,754


2007

Method for incremental, timing-driven, physical-synthesis optimization
Charles J Alpert, Arvind K Karandikar, Zhuo Li, Gijoon Nam, David A Papa, Chin Ngai Sze
US Patent App. 11/866,231

Method and Apparatus for Congestion Based Physical Synthesis
C J Alpert, A K Karandikar, Z Li, C N Sze
US Patent App. 11/748,514


2006

Method to reduce the wirelength of analytical placement techniques by modulation of spreading forces vectors
C J Alpert, G J Nam, H Ren, P G Villarrubia, N Viswanathan
US Patent App. 11/531,322

Stability metrics for placement to quantify the stability of placement algorithms
C J Alpert, G J Nam, P G Villarrubia, M C Yildiz
US Patent 7,073,144


2003

Hybrid quadratic placement with multiple linear system solvers
C J Alpert, G J Nam, P G Villarrubia
US Patent App. 10/687,246

Analytical constraint generation for cut-based global placement
C J Alpert, G J Nam, P G Villarrubia
US Patent 6,671,867