Daniel C Edelstein  Daniel C Edelstein photo       

contact information

IBM Fellow; Manager: Processes, Materials, & Integration
Thomas J. Watson Research Center, Yorktown Heights, NY USA
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Professional Associations

Professional Associations:  IEEE Electron Devices Society (EDS)  |  National Academy of Engineering


2008

Interface engineering for high interfacial strength between SiCOH and porous SiCOH interconnect dielectrics and diffusion caps
A Grill, D Edelstein, M Lane, V Patel, S Gates, D Restaino, S Molis
Journal of Applied Physics103, 054104, 2008

Performance and reliability of airgaps for advanced BEOL interconnects
S Nitta, D Edelstein, S Ponoth, L Clevenger, X Liu, T Standaert
Interconnect Technology Conference, 2008. IITC 2008. International, pp. 191--192


2007

Enhanced Cracking Resistance of Plasma Deposited Low k SiCOH Films with Nano Imbedded Layers Insertion
S V Nguyen, E Liniger, K Ida, B Herbst, K Malone, N Klymko, S Cohen, E Simonyi, S Lane, C Dziobkowski, others
2007 - electrochem.org

Non-Poisoning Dual Damascene Patterning Scheme for Low-k and Ultra Low-k BEOL
W Cote, D Edelstein, C Bunke, P Biolsi, W Wille, H Baks, R Conti, T Dalton, T Houghton, W Li
Advanced Metallization Conference 2006(AMC 2006), 2007

A Porous SiCOH Dielectric with k= 2. 4 for High Performance BEOL Interconnects
SM Gates, A Grill, C Dimitrakopoulos, D Restaino, M Lane, V Patel, S Cohen, E Simonyi, E Linger, Y Ostrovski, others
Advanced Metallization Conference 2006(AMC 2006), 2007

Optimization of silicon technology for the IBM System z9
T Ivers, S Narasimha, TB Faure, JH Rankin, DA Grosch, MD Knox, DC Edelstein, M Khare, GB Bronner, HJ Nam, others
IBM Journal of Research and Development 51(1-2), 5--18, Citeseer, 2007


2006

Edge seal for integrated circuit chips
D C Edelstein, L M Nicholson
US Patent 7,098,544, 2006 - Google Patents, Google Patents
US Patent 7,098,544

Determination of the thermal conductivity of composite low-k dielectrics for advanced interconnect structures
F Chen, J Gill, D Harmon, T Sullivan, A Strong, B Li, H Rathore, D Edelstein
Microelectronics Reliability 46(2-4), 232--243, Elsevier, 2006

A 45 nm CMOS node Cu/Low-k/Ultra Low-k PECVD SiCOH (k= 2.4) BEOL technology
S Sankaran, S Arai, R Augur, M Beck, G Biery, T Bolom, G Bonilla, O Bravo, K Chanda, M Chae, others
Electron Devices Meeting, 2006. IEDM'06. International, pp. 1--4

High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
S Narasimha, K Onishi, HM Nayfeh, A Waite, M Weybright, J Johnson, C Fonseca, D Corliss, C Robinson, M Crouse, others
Electron Devices Meeting, 2006, pp. 1--4


2005

Extendibility of PVD barrier/seed for BEOL Cu metallization
C C Yang, D Edelstein, L Clevenger, A Cowley, J Gill, K Chanda, A Simon, T Dalton, B Agarwala, E Cooney III, others
Interconnect Technology Conference, 2005, pp. 135--137

Silicon Carrier with Deep Through-Vias, Fine Pitch Wiring and Through Cavity for Parallel Optical Transceiver
C. S. Patel, C. K. Tsang, C. Schuster, F. E. Doany, H. Nyikal, C. W. Baks, R. Budd, L. P. Buchwalter, P. S. Andry, D. F. Canaperi, D. C. Edelstein, R. Horton, J. U. Knickerbocker, T. Krywanczyk, Y. H. Kwark, K. T. Kwietniak, J. H. Magerlein, J. Rosner, E.
Proceedings Electronic Components and Technology, 2005. ECTC '05., pp. 1318-1324


2004

STRUCTURES D'INTERCONNEXION DANS DES DISPOSITIFS DE CIRCUITS INTEGRES
W WILLE, D EDELSTEIN, W COTE, P BIOLSI, J FRITCHE
WO Patent 2,004,114,396, 2004
WO Patent 2,004,114,396

INTERCONNECT STRUCTURES IN INTEGRATED CIRCUIT DEVICES
W Wille, D Edelstein, W Cote, P Biolsi, J Fritche, A Upham
freepatentsonline.com, 2004

Optimization of SiCOH dielectrics for integration in a 90nm CMOS technology
A. Grill, D. Edelstein, D. Restaino, M. Lane, S. Gates, E. Liniger, T. Shaw, XH Liu, D. Klaus, V. Patel, others
Interconnect Technology Conference, 2004. Proceedings of the IEEE 2004 International, pp. 54--56

Low-k BEOL mechanical modeling
X H Liu, M W Lane, T M Shaw, E G Liniger, R R Rosenberg, D C Edelstein
Proc, pp. 361--367, 2004

Chip-to-package interaction for a 90 nm Cu/PECVD low-k technology
W Landers, D Edelstein, L Clevenger, C Das, C C Yang, T Aoki, F Beaulieu, J Casey, A Cowley, M Cullinan, others
Interconnect Technology Conference, 2004, pp. 108--110

Measurements of effective thermal conductivity for advanced interconnect structures with various composite low-k dielectrics
F Chen, J Gill, D Harmon, T Sullivan, B Li, A Strong, H Rathore, D Edelstein, C C Yang, A Cowley, others
2004 IEEE International Reliability Physics Symposium Proceedings, 2004, pp. 68--73

Reliability, yield, and performance of a 90 nm SOI/Cu/SiCOH technology
D Edelstein, C Davis, L Clevenger, M Yoon, A Cowley, T Nogami, H Rathore, B Agarwala, S Arai, A Carbone, others
Interconnect Technology Conference, 2004, pp. 214--216

Comprehensive reliability evaluation of a 90 nm CMOS technology with Cu/PECVD low-k BEOL
D Edelstein, H Rathore, C Davis, L Clevenger, A Cowley, T Nogami, B Agarwala, S Arai, A Carbone, K Chanda, others
Reliability Physics Symposium Proceedings, 2004, pp. 316--319


2003

Chemical-mechanical planarization of metallurgy
V Brusic, D C Edelstein, P M Feeney, W Guthrie, M Jaso, F B Kaufman, N Lustig, P Roper, K Rodbell, D B Thompson, others
US Patent 6,632,377, 2003 - freepatentsonline.com
US Patent 6,632,377

Copper BEOL interconnects for silicon CMOS logic technology
Satya V Nitta, Sampath Purushothaman, James G Ryan, Daniel C Edelstein, Panayotis Andricacos, Chao-Kun Hu, Thomas M Shaw, Robert Rosenberg, James R Lloyd
Interconnect Technology and Design for Gigascale Integration, pp. 35--65, Springer, 2003


2002

Thin film metal barrier for electrical interconnections
N C Cyril Jr, P W Dehaven, D C Edelstein, D P Klaus, M P James III, C L Stanis, C E Uzoh
freepatentsonline.com, Google Patents, 2002
US Patent App. 09/759,258

Method for preparing a conductive pad for electrical connection and conductive pad formed
C J Sambucetti, D C Edelstein, J G Gaudiello, J M Rubino, G Walker
US Patent 6,335,104, 2002 - Google Patents, Google Patents
US Patent 6,335,104

Chemical-mechanical planarization of barriers or liners for copper metallurgy
W J Cote, D C Edelstein, N E Lustig
US Patent App. 10/051,135, 2002 - Google Patents, Google Patents
US Patent App. 10/051,135

Post-fuse blow corrosion prevention structure for copper fuses
T H Daubenspeck, D C Edelstein, R M Geffken, W T Motsiff, A K Stamper, S H Voldman
US Patent App. 10/254,277, 2002 - Google Patents, Google Patents
US Patent App. 10/254,277


2001

Planar integrated circuit interconnect
B Dirahoui, D C Edelstein, R C Greenlese, H C Jones
US Patent 6,281,583, 2001 - Google Patents, Google Patents
US Patent 6,281,583

Adhesion of silicon carbide films
D R Cote, D C Edelstein, J A Fitzsimmons, T H Ivers, P C Jamison, E Levine
US Patent 6,252,295, 2001 - Google Patents, Google Patents
US Patent 6,252,295

Chemical-mechanical planarisation of copper
V Brusic, D C Edelstein, P M Fenney, W Guthrie, M Jaso, F B Kaufman, N Lustig, P Roper, K Rodbell, D B Thompson, others
freepatentsonline.com, 2001

Thin metal barrier for electrical interconnections
C Cabral Jr, P W DeHaven, D C Edelstein, D P Klaus, J M Pollard III, C L Stanis, C E Uzoh
US Patent ..., 2001 - Google Patents, Google Patents
US Patent 6,291,885

A high performance liner for copper damascene interconnects
D Edelstein, C Uzoh, C Cabral, P DeHaven, P Buchwalter, A Simon, E Cooney, S Malhotra, D Klaus, H Rathore, others
Interconnect Technology Conference, 2001, pp. 9--11

On-chip wiring design challenges for gigahertz operation
Alina Deutsch, Paul W Coteus, GERARD V Kopcsay, HOWARD H Smith, CHRISTOPHER W Surovic, BYRON L Krauter, DANIEL C Edelstein, PL Restle
Proceedings of the IEEE 89(4), 529--555, IEEE, 2001


2000

Method of forming an integrated circuit spiral inductor with ferromagnetic liner
J N Burghartz, D C Edelstein, C V Jahnes, C E Uzoh
US Patent 6,054,329, 2000 - Google Patents, Google Patents
US Patent 6,054,329

Integrated circuit spiral inductor
J N Burghartz, D C Edelstein, C V Jahnes, C E Uzoh
US Patent 6,114,937, 2000 - Google Patents, Google Patents
US Patent 6,114,937

Process and diffusion baffle to modulate the cross sectional distribution of flow rate and deposition rate
D C Edelstein
US Patent 6,106,687, 2000 - Google Patents, Google Patents
US Patent 6,106,687

C OPPER M ETALLIZATION F OR H IGH P ERFORMANCE S ILICON T ECHNOLOGY
R Rosenberg, DC Edelstein, C K Hu, KP Rodbell
Annual Review of Materials Science 30(1), 229--262, Annual Reviews, 2000

A high performance 0.13 $\mu$m copper BEOL technology with low-k dielectric
RD Goldblatt, B Agarwala, MB Anand, EP Barth, GA Biery, ZG Chen, S Cohen, JB Connolly, A Cowley, T Dalton, others
Interconnect Technology Conference, 2000, pp. 261--263


1999

Method of forming an integrated circuit toroidal inductor
J N BURGHARTZ, D C EDELSTEIN, C V JAHNES, C E UZOH
v3.espacenet.com, 1999

Advanced interconnects and contacts: symposium held April 5-7, 1999, San Francisco, California, USA
D C Edelstein, K N Tu, M C Ozturk, E J Weitzman
Materials Research Society, Materials Research Society, 1999

Copper Interconnect Technology in Semiconductor Manufacturing
D C Edelstein, R W Megivern, E Walton
Electrochemical processing in ULSI fabricatrion and semiconductor/metal deposition II: proceedings of the International Symposium, pp. 1, 1999

Integrated circuit inductor
J N Burghartz, D C Edelstein, C V Jahnes, C E Uzoh
US Patent 5,884,990, 1999 - Google Patents, Google Patents
US Patent 5,884,990

Topography monitor
D C Edelstein, G A Biery
US Patent 5,952,674, 1999 - Google Patents, Google Patents
US Patent 5,952,674

On-chip wiring design challenges for Ghz operation
A Deutsch, H Smith, GV Kopcsay, DC Edelstein, PW Coteus
Electrical Performance of Electronic Packaging, 1999, 45--48


1998

Integrated circuit toroidal inductor
J N Burghartz, D C Edelstein, C V Jahnes, C E Uzoh
US Patent 5,793,272, 1998 - Google Patents, Google Patents
US Patent 5,793,272

RF circuit design aspects of spiral inductors on silicon
J N Burghartz, DC Edelstein, M Soyuer, HA Ainspan, K A Jenkins
IEEE Journal of Solid-State Circuits 33(12), 2028--2034, Citeseer, 1998

A High-Performance Sub-0.25 (jm CMOS Technology with Multiple Thresholds and Copper Interconnects
L S R S J Adkisson, K B G Biery, W C E C D Edelstein, J Ellis-Monaghan, E Eld, D F R G R Goldblatt, N Greco, C Guenther, J H J H D Kiesling, L Lin, others
1998 Symposium on VLSI Technology: digest of technical papers: June 9-11, 1998, Honolulu, pp. 18

An evaluation of Cu wiring in a production 64 Mb DRAM
W Cote, G Costrini, D Edelstein, C Osborn, D Poindexter, V Sardesai, G Bronner
VLSI Technology, 1998, pp. 24--25

Copper ULSI interconnect technology
D Edelstein
Advanced Interconnects and Contact Materials and Processes for Future Integrated Circuits as held at the 1998 MRS Spring Meeting, pp. 1999

Cu Interconnects
D Edelstein, C Osborn, D Poindexter, V Sardesai, G Bronner, IBM Semicon-ductor, I Motorola, TX Austin
1998 Symposium on VLSI Technology: digest of technical papers: June 9-11, 1998, Honolulu, pp. 21

A high-performance sub-0.25 $\mu$m CMOS technology with multiplethresholds and copper interconnects
L Su, R Schulz, J Adkisson, K Beyer, G Biery, W Cote, E Crabbe, D Edelstein, J Ellis-Monaghan, E Eld, others
VLSI Technology, 1998, pp. 18--19

Copper dual damascene wiring for sub-0.25 $\mu$m CMOS technology
J Heidenreich, D Edelstein, R Goldblatt, W Cote, C Uzoh, N Lustig, T McDevitt, A Stamper, A Simon, J Dukovic, others
Interconnect Technology Conference, 1998, pp. 151--153

Copper chip technology
D C Edelstein
Proceedings of SPIE, pp. 8, 1998

Functional high-speed characterization and modeling of a six-layercopper wiring structure and performance comparison with aluminum on-chipinterconnections
A Deutsch, H Harrer, CW Surovic, G Hellner, DC Edelstein, RD Goldblatt, GA Biery, NA Greco, DM Foster, E Crabbe, others
Electron Devices Meeting, 1998, pp. 295--298

Spiral and solenoidal inductor structures on silicon usingCu-damascene interconnects
DC Edelstein, JN Burghartz
Interconnect Technology Conference, 1998, pp. 18--20


1997

Tech. Digest, IEEE Intl. Electron Devices Conferences, 773 (1997)
DC Edelstein
IBM Res. Mag4, 16, 1997

IBM Semiconductor Research and Development Center
D Edelstein, others
Technical Digest of, 772--776, 1997

Diamondlike Carbon Materials as Low-k Dielectrics for Multilevel Interconnects in ULSI
A Grill, V Patel, KL Saenger, C Jahnes, SA Cohen, AG Schrott, DC Edelstein, JR Paraszczak
MATERIALS RESEARCH SOCIETY SYMPOSIUM PROCEEDINGS, pp. 155--164, 1997

Spiral inductors and transmission lines in silicon technology usingcopper-damascene interconnects and low-loss substrates
JN Burghartz, DC Edelstein, KA Jenkiin, YH Kwark
IEEE Transactions on Microwave Theory and Techniques 45(10 Part 2), 1961--1968, 1997

Full copper wiring in a sub-0.25 mm CMOS ULSI technology
D Edelstein, J Heidenreich, R Goldblatt, W Cote, C Uzoh, N Lustig, P Roper, T McDevitt, W Motsiff, A Simon, others
Proceedings of the IEEE International Electron Devices Meeting, pp. 773--776, 1997


1996

The Wiring Challenge: Complexity and Crowding
TP Smith, TR Dinger, DC Edelstein, JR Paraszczak, TH Ning
NATO ASI SERIES E APPLIED SCIENCES323, 45--56, KLUWER ACADEMIC PUBLISHERS, 1996

Watson Research Center,“
G Smith, TJ IBM
Additive Extensions of a Quantum Channel, 978--1, 1996

IBM-Research Division,“Diamondlike Carbon Materials as Low-k Dielectrics For Multilevel Interconnects in ULSI.” 10 pgs
A Grill, V Patel, KL Saenger, C Jahnes, SA Cohen, AG Schrott, DC Edelstein, JR Paraszczak
1996 - Fall, Fall


1995

VLSI on-chip interconnection performance simulations and measurements
DC Edelstein, GA Sai-Halasz, YJ Mii
IBM Journal of Research and Development 39(4), 383--402, [Armonk, NY]: International Business Machines Corp., 1995


1993

Electrical and physical properties of high-Ge-content Si/SiGe p-type quantum wells
RA Kiehl, PE Batson, JO Chu, DC Edelstein, FF Fang, B Laikhtman, DR Lombardi, WT Masselink, BS Meyerson, JJ Nocera, others
Physical Review B 48(16), 11946--11959, APS, 1993

High performance dielectrics and processes for ULSI interconnectiontechnologies
J Paraszczak, D Edelstein, S Cohen, E Babich, J Hummel
Electron Devices Meeting, 1993, pp. 261--264


1992

Optical Measurement Of Internal Logic Patterns In A Flip-chip Mounted Silicon SRAM Integrated Circuit
HK Heinrich, N Pakdaman, JL Prince, G Jordy, M Belaidi, R Franch, DC Edelstein
Lasers and Electro-Optics Society Annual Meeting, 1992, pp. 121--122

Aminoguanidine ameliorates albuminuria in diabetic hypertensive rats
D Edelstein, M Brownlee
Diabetologia 35(1), 96--97, Springer, 1992


1991

Three-dimensional capacitance modeling of advanced multilayer interconnection technologies
D C Edelstein
Society of Photo-Optical Instrumentation Engineers (SPIE) Conference Series, pp. 352--360, 1991


1990

3-D capacitance modeling of advanced multilayer interconnection technologies
DC Edelstein, AP DeFonzo
International Symposium on Advances in Interconnection and Packaging, pp. 352--360, 1990


Year Unknown


FP 16.1: RF Circuit Design Aspects of Spiral Inductors on Silicon
J Burghartz, D Edelstein, M Soyuer, H Ainspan, K Jenkins
iroi.seu.edu.cn, 0

Lightly porous SiCOH 2.7 dielectric film development for 65/45/32 nm advanced nanoelectronic CMOS devices
S Nguyen, V McGahay, M Sherwood, N Klymko, S Cohen, E Simonyi, H Shobha, D Restaino, A Grill, S Lane, others
electrochem.org, 0

Optimization of silicon technology for the IBM System z9-Author Bios
D J Poindexter, S R Stiffler, P T Wu, P D Agnello, T Ivers, S Narasimha, T B T Faure, J H Rankin, D A Grosch, M D Knox, others
DJ Poindexter, SR Stiffler, PT Wu, PD ..., 0

Optimization of silicon technology for the IBM System z9-References
DJ Poindexter, SR Stiffler, PT Wu, PD Agnello, T Ivers, S Narasimha, TB Faure, JH Rankin, DA Grosch, MD Knox, others
DJ Poindexter, SR Stiffler, PT Wu, PD ..., 0

Copper Resistivity in Electrodeposited Dual Damascene Interconnects--An Integrated Circuit Perspective
N Lustig, B Baker-O’Neal, P Flaitz, T Standaert, P DeHaven, A Simon, T Ko, S Grunow, J Werking, S Greco, others
... S Sankaran, H Deligianni, D Edelstein , TJ IBM ..., 0

Physical, electrical, and reliability characterization of Ru for Cu interconnects
C C Yang, T Spooner, S Ponoth, K Chanda, A Simon, C Lavoie, M Lane, C K Hu, E Liniger, L Gignac, others
Interconnect Technology Conference, 2006 International, pp. 187--190