Augusto J. Vega  Augusto J. Vega photo       

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Research Scientist : Computer Science
Thomas J. Watson Research Center, Yorktown Heights, NY USA
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Professional Associations:  ACM SIGARCH  |  IEEE Computer Society

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2017

Thermal model for embedded two-phase liquid cooled microprocessor
Parida, Pritish R and Sridhar, Arvind and Vega, Augusto and Schultz, Mark D and Gaynes, Michael and Ozsun, Ozgur and McVicker, Gerard and Brunschwiler, Thomas and Buyuktosunoglu, Alper and Chainer, Timothy
Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 2017 16th IEEE Intersociety Conference on, pp. 441--449
Abstract

Secure swarm intelligence: A new approach to many-core power management
Vega, Augusto and Buyuktosunoglu, Alper and Bose, Pradip
Low Power Electronics and Design (ISLPED, 2017 IEEE/ACM International Symposium on, pp. 1--6
Abstract


2016

Characterization and mitigation of power contention across multiprogrammed workloads
Sasaki, Hiroshi and Buyuktosunoglu, Alper and Vega, Augusto and Bose, Pradip
Workload Characterization (IISWC), 2016 IEEE International Symposium on, pp. 1--10

Rugged Embedded Systems: Computing in Harsh Environments
Vega, Augusto and Bose, Pradip and Buyuktosunoglu, Alper
2016 - books.google.com, Morgan Kaufmann

Embedded two phase liquid cooling for increasing computational efficiency
Parida, Pritish R and Vega, Augusto and Buyuktosunoglu, Alper and Bose, Pradip and Chainer, Timothy
Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 2016 15th IEEE Intersociety Conference on, pp. 326--336

Mitigating power contention: a scheduling based approach
Sasaki, Hiroshi and Buyuktosunoglu, Alper and Vega, Augusto and Bose, Pradip
IEEE Computer Architecture Letters, IEEE, 2016


2015

Resilient mobile cognition: Algorithms, innovations, and architectures
Viguier, Raphael and Lin, C-C and Swaminathan, Karthik and Vega, Augusto and Buyuktosunoglu, Alper and Pankanti, Sharathchandra and Bose, Pradip and Akbarpour, H and Bunyak, Filiz and Palaniappan, Kannappan and others
Computer Design (ICCD), 2015 33rd IEEE International Conference on, pp. 728--731

Power-efficient embedded processing with resilience and real-time constraints
Wang, Liang and Vega, Augusto J and Buyuktosunoglu, Alper and Bose, Pradip and Skadron, Kevin
Low Power Electronics and Design (ISLPED), 2015 IEEE/ACM International Symposium on, pp. 231--236

Resilient, UAV-embedded real-time computing
Vega, Augusto and Lin, Chung-Ching and Swaminathan, Karthik and Buyuktosunoglu, Alper and Pankanti, Sharathchandra and Bose, Pradip
Computer Design (ICCD), 2015 33rd IEEE International Conference on, pp. 736--739


2014

Guest Editorial: Robust and energy-secure systems
Vega, Augusto and Sethumadhavan, Simha and Mitra, Subhasish
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 4(2), 165--168, IEEE, 2014

Special Series on Harsh Chips [Guest Editors' introduction]
Vega, Augusto and Buyuktosunoglu, Alper and Bose, Pradip
IEEE Micro 34(6), 6--7, IEEE, 2014

Resilience and real-time constrained energy optimization in embedded processor systems
Wang, Liang and Rivers, Jude A and Gupta, Meeta S and Vega, Augusto J and Buyuktosunoglu, Alper and Bose, Pradip and Skadron, Kevin
Workshop on Silicon Errors in Logic-System Effects (SELSE), 2014


2013

Performance and power optimizations in chip multiprocessors for throughput-aware computation
Vega, Augusto
Ph.D. Thesis, Universitat Politecnica de Catalunya (UPC), 2013

Crank it up or dial it down: coordinated multiprocessor frequency and folding control
Vega, Augusto and Buyuktosunoglu, Alper and Hanson, Heather and Bose, Pradip and Ramani, Srinivasan
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 210--221, 2013

SMT-centric power-aware thread placement in chip multiprocessors
Vega, Augusto and Buyuktosunoglu, Alper and Bose, Pradip
Parallel Architectures and Compilation Techniques (PACT), 2013 22nd International Conference on, pp. 167--176

SMT switch: Software Mechanisms for Power Shifting
Priyanka Tembey, Augusto Vega, Alper Buyuktosunoglu, Dilma Da Silva, Pradip Bose
Computer Architecture Letters 12(2), 67--70, IEEE, 2013


2012

On the simulation of large-scale architectures using multiple application abstraction levels
A. Rico, F. Cabarcas, C. Villavieja, M. Pavlovic, A. Vega, Y. Etsion, A. Ramirez, M. Valero
ACM Transactions on Architecture and Code Optimization (TACO) 8(4), 36, ACM, 2012

Architectural perspectives of future wireless base stations based on the IBM PowerEN ? processor
A. Vega, P. Bose, A. Buyuktosunoglu, J. Derby, M. Franceschini, C. Johnson, R. Montoye
2012 - doi.ieeecomputersociety.org, IEEE

Power Management of Multi-Core Chips: Challenges and Pitfalls
Pradip Bose, Alper Buyuktosunoglu, John A. Darringer, Meeta S. Gupta, Michael B. Healy, Hans Jacobson, Indira Nair, Jude A. Rivers, Jeonghee Shin, Augusto Vega, Alan J. Weger
Design, Automation & Test in Europe Conference & Exhibition, pp. 977--982, 2012

Power-aware thread placement in SMT/CMP architectures
Augusto Vega, Pradip Bose, Alper Buyuktosunoglu
Proc. of the 4th Workshop on Energy Efficient Design (WEED), Portland, OR, USA, 2012

Architectural perspectives of future wireless base stations based on the IBM PowerEN™ processor
Augusto Vega, Pradip Bose, Alper Buyuktosunoglu, Jeff Derby, Michele Franceschini, Charles Johnson, Robert Montoye
High Performance Computer Architecture (HPCA), 2012 IEEE 18th International Symposium on, pp. 1--10


2011

Breaking the bandwidth wall in chip multiprocessors
A. Vega, F. Cabarcas, A. Ramirez, M. Valero
Embedded Computer Systems (SAMOS), 2011 International Conference on, pp. 255--262


2010

Scalable simulation of decoupled accelerator architectures
Rico, Alejandro and Cabarcas, Felipe and Quesada, Antonio and Pavlovic, Milan and Vega, Augusto Javier and Villavieja, Carlos and Etsion, Yoav and Ramirez, Alex
Universitat Politecnica de Catalunya, Tech. Rep. UPC-DACRR-2010-14

Comparing last-level cache designs for CMP architectures
A. Vega, A. Rico, F. Cabarcas, A. Ramirez, M. Valero
Proceedings of the Second International Forum on Next-Generation Multicore/Manycore Technologies, pp. 2, 2010

Scalable simulation of decoupled accelerator architectures
A. Rico, F. Cabarcas, A. Quesada, M. Pavlovic, AJ Vega, C. Villavieja, Y. Etsion, A. Ramirez
Universitat Politecnica de Catalunya, Tech. Rep. UPC-DACRR-2010-14

Archexplorer for automatic design space exploration
V. Desmet, S. Girbal, A. Ramirez, O. Temam, A. Vega
Micro, IEEE 30(5), 5--15, IEEE, 2010