Yutaka Nakamura  Yutaka Nakamura photo       

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Research Staff Member
Research - Tokyo
  +81dash50dash3150dash3535

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2014

Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100x Speedup in Time-to-Solution and ~100,000x Reduction in Energy-to-Solution
Andrew S. Cassidy, Rodrigo Alvarez-Icaza, Filipp Akopyan, Jun Sawada, John V. Arthur, Paul A. Merolla, Pallab Datta, Marc Gonzalez Tallada, Brian Taba, Alexander Andreopoulos, Arnon Amir, Steven K. Esser, Jeff Kusnitz, Rathinakumar Appuswamy, Chuck Haymes
IEEE Supercomputing, 2014

A Million Spiking-Neuron Integrated Circuit with a Scalable Communication Network and Interface
Paul A. Merolla, John V. Arthur, Rodrigo Alvarez-Icaza, Andrew S. Cassidy, Jun Sawada, Filipp Akopyan, Bryan L. Jackson, Nabil Imam, Chen Guo, Yutaka Nakamura, Bernard Brezzo, Ivan Vo, Steven K. Esser, Rathinakumar Appuswamy, Brian Taba, Arnon Amir, Myron
Science, 2014


2011

A 4R2W Register File for a 2.3GHz Wire-Speed POWERTM Processor with Double-Pumped Write Operation
Ditlow, Gary S. ; Montoye, R.K. ; Storino, S.N. ; Dance, S.M. ; Ehrenreich, S. ; Fleischer, B.M. ; Fox, T.W. ; Holmes, K.M. ; Mihara, J. ; Nakamura, Y. ; Onishi, S. ; Shearer, R. ; Wendel, D. ; Chang, L
IEEE ISSCC, 2011


2008

An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in HP Caches
Chang, L. ; Montoye, R.K. ; Nakamura, Y. ; Batson, K.A. ; Eickemeyer, R.J. ; Dennard, R.H. ; Haensch, W. ; Jamsek, D
IEEE Journal of Solid State Circuits, 2008


2007

A 5.3GHz 8T-SRAM with Operation Down to 0.41V in 65nm CMOS
Chang, L. ; Nakamura, Y. ; Montoye, R.K. ; Sawada, J. ; Martin, A.K. ; Kinoshita, K. ; Gebara, F.H. ; Agarwal, K.B. ; Acharyya, D.J. ; Haensch, W. ; Hosokawa, K. ; Jamsek, D
IEEE VLSI Symposium of Circuits, 2007


1997

An eight-bit prefetch circuit for high-bandwidth DRAM's
Sunaga, T. ; Hosokawa, K. ; Nakamura, Y. ; Ichinose, M. ; Igarashi, Y.
IEEE Journal of Solid State Circuits, 1997


1995

A full bit prefetch architecture for synchronous DRAM's
Sunaga, T. ; Hosokawa, K. ; Nakamura, Y. ; Ichinose, M. ; Moriwaki, A. ; Kakimi, S. ; Kato, N
IEEE Journal of Solid State Circuits, 1995




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