Atsuya Okazaki  Atsuya Okazaki photo       

contact information

Research Staff Member
IBM Research - Tokyo
  +81dash50dash3150dash3712

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Professional Associations

Professional Associations:  IEEE Computer Society


2017

Hardware technologies for neuromorphic computing
Atsuya Okazaki
Journal of the Robotics Society of Japan 35(3), 2017


2014

Non-intrusive Scalable Memory Access Tracer
Nobuyuki Ohba, Seiji Munetoh, Atsuya Okazaki, Yasunao Katayama
QEST 2014

Hybrid Main Memory Using Electrically- and Optically-Attached Memories
Atsuya Okazaki, Nobuyuki Ohba, Yasunao Katayama
Proceedings of the IEEE Symposium on Low-Power and High-Speed Chips (COOLChips-XVII) 2014


2013

Wireless Crossbar Switch Architecture for mmWave Data Center Applications
Y. Katayama, K. Takano, Y. Kohda, D. Nakano, A. Okazaki
GSMM 2013

Software-defined massive multicore networking via freespace optical interconnect
Y. Katayama, A. Okazaki, N. Ohba
Computing Frontiers 2013

Intelligent Memory Module Architecture for Energy-Efficient Big Data Processing
A. Okazaki, S. Munetoh, N. Ohba, Y. Katayama
Proceedings of the IEEE Symposium on Low-Power and High-Speed Chips (COOLChips-XVI), 2013


2011

Universal optical multi-drop bus for heterogeneous memory architecture
A. Okazaki, Y. Katayama, S. Munetoh
Computing Frontiers 2011


2009

Optical Multi-Drop Memory Architecture for Multi-Core Processors
A. Okazaki, Y. Katayama
Proceedings of the IEEE Symposium on Low-Power and High-Speed Chips (COOLChips-XII), 2009


2007

Optical Interconnect Opportunities for Future Server Memory Systems
Y. Katayama and A. Okazaki
Proceedings of the IEEE 13th International Symposium on High Performance Computer Architecture (HPCA-13), 2007

Performance Analysis on Optically-enabled SMP Servers
A. Okazaki, Y. Katayama
IPSJ SIG Notes Vol.2007, No.80 2007-HPC-111-(47)


2006

Secure Processor Architecture for High-Speed Verification of Memory Integrity
A. Okazaki, N. Masaki, S. Yamashita
IPSJ SIG Notes, Vol.2006, No.127 2006-ARC-170-(3)


2004

Certification of Program Execution by Tamper Resistant CPU
A. Okazaki, M. Nakanishi, S. Yamashita, K. Watanabe
IEICE Technical Report, ISEC2004-37

Blocking execution of malware code by CPU
A. Okazaki, M. Nakanishi, S. Yamashita, K. Watanabe
Computer Security Symposium 2004 (CSS2004)