SynTunSys       

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 Matthew M. Ziegler photo

SynTunSys - overview


Advanced logic and physical synthesis tools provide a vast number of tunable parameters that can significantly impact physical design quality, but the complexity of the parameter design space requires intelligent search algorithms. To fully utilize the optimization potential of these tools, we propose SynTunSys, a system that adds a new level of abstraction between designers and design tools for managing the design space exploration process. SynTunSys takes control of the synthesis-parameter tuning process, i.e., job submission, results analysis, and next-step decision making, by automating a key portion of a human designer’s decision process. SynTunSys has been used during the design of IBM 22nm processors, i.e., the POWER8 server and the z13 mainframe chips. SynTunSys provided significant savings in human design effort and achieved a quality of results beyond what human designers alone could achieve, yielding on average a 36% improvement in total negative slack and a 7% power reduction.

References:

 

Matthew M. Ziegler, Hung-Yi Liu, George Gristede, Bruce Owens, Ricardo Nigaglioni, and Luca P. Carloni, "A Synthesis-Parameter Tuning System for Autonomous Design-Space Exploration"
Design Automation & Test in Europe, 2016 (DATE16)

--- "A Scalable Black-Box Optimization System for Auto-Tuning VLSI Synthesis Programs"
1st Workshop on RESource Awareness and Application Auto-tuning in Adaptive and heterogeNeous compuTing (co-located w/ DATE), 2016

--- "A Scalable Black-Box Optimization System for Automating VLSI Design Decisions"
New York Academy of Sciences' 10th Annual Machine Learning Symposium, 2016

--- "A Synthesis-Parameter Tuning System for Autonomous Design-Space Exploration"
Design Automation Conference - work-in-progress session, 2015 (DAC15)

Matthew M. Ziegler, Hung-Yi Liu, and Luca P. Carloni, "Scalable Auto-Tuning of Synthesis Parameters for Optimizing High-Performance Processors"
International Symposium on Low-Power Electronic Devices, ISLPED16 (to appear)

Mohd Anwar, Sourav Saha, Matthew M. Ziegler, Lakshmi Reddy
"Early Scenario Pruning for Efficient Design Space Exploration in Physical Synthesis"
International Conference on VLSI Design, 2016 (VLSID16).

Matthew M. Ziegler, George D. Gristede, Victor V. Zyuban, “Power Reduction by Ag-gressive Synthesis Design Space Exploration,” ISLPED 2013.