Design Automation - overview
Design Automation at IBM Research has a long history of innovation. From logic synthesis in the early days to statistical timing in recent times, we have been leading IBM and the design automation industry at large into exciting new areas of research that eventually become game changers for chip design. Our primary goal is to enable design of IBM's high-performance hardware products with high efficiency and affordability, while dealing with increasing system complexity, aggressive time to revenue schedules, and a growing number of conflicting acceptance criteria (power, performance, yield, cost, reliability, etc.) through innovative research in design automation.
Our research agenda has adapted to the evolving needs of the design community. When design automation was in its formative years, we focused on creating point tools and developing algorithms in logic optimization and verification, timing analysis, placement, and routing. As the industry reaped the benefits of Moore's Law and technology nodes and chip designs increased in complexity, we emphasized integration of point tools (e.g. logic synthesis and placement) and building design flows. Today, chip design is so complex that it is rapidly becoming unaffordable, design space exploration is becoming intractable with the advent of many core and 3D integration, and technology nodes are nearly impossible to develop and use due to increasing variability. Our strategy is to develop efficient methodologies and design flows that enable the design team to accomplish more with less resources without compromising the quality of results, enable evaluation of design options for complex 2D and 3D chips using reliability metrics, analyze and mitigate variability to enhance parametric yield, and parallelize EDA applications to fully leverage multi-core machines.
In addition to serving IBM's System and Technology group, our team is tireless in serving and building the external design automation community. We actively participate in conferences and workshops on design automation by serving on organizing, executive and technical program committees, and by contributing papers and presentations. A lot of us are active members of IEEE and ACM - some of us are IEEE fellows. Our department includes an ACM distinguished lecturer, a Women in EDA Award winner, and an IEEE Industrial Pioneer Award recipient. We also collaborate with the academic community, support academic research through SRC and faculty awards, and host academic visitors and summer interns at our sites.
Our team is mainly located in 2 locations: the Thomas J. Watson Research Center in Yorktown Heights, New York, and the Austin Research Lab in Austin, Texas.
- BEAM (Bugs Errors And Mistakes)
- Chip Planner
- FPGA Systems
- Statistical Timing Analysis and At-speed Test
- Statistical Performance Path Test for Yield Improvement and Margin Reduction
- Technology-Circuit Co-optimization Productivity
- Buffer Optimization
- Hardware Murphi
- MASH (Migration Assitant Shape Handler)
- NOVA - Full Chip Power Supply Noise Analysis
- Virtual Fab