Thomas J. Watson Research Center, Yorktown Heights, NY USA
I'm a Research Staff Member at the IBM T.J. Watson Research Center in Yorktown Heights, New York.
I have received the MS degree in Physics from Moscow Institute of Physics and Technology in 1989, and the PhD degree in Physics from SUNY Stony Brook in 1997.
At Stony Brook I worked on the design and testing of superconductor integrated circuits based on Josephson junctions. I started at IBM on March 17, 1999, working on the design and testing of high-speed digital and mixed-signal communication circuits for optical and channel-limited wireline communications.
I was part of the team that pioneered the DPLL research at IBM in 2005. The DPLLs are now used in a number of IBM products, including P7 microprocessor and many others.
2011 and 2013 IBM Outstanding Technical Achievement Awards: “Development of Digital PLL Technology and Its Establishment in IBM Product Roadmaps”
2013 IBM Outstanding Technical Achievement Award: “Technologies for Terabit/s Optical Transceivers”
The 30 Gb/s VCSEL-based optical link was highlighted in Electronics Letters interview (2011) and the 40 Gb/s link was presented at OFC 2012, 56 Gb/s link reported in 2013.
I also work on circuits for Silicon Photonics.
2012 IBM Outstanding Technical Achievement Award: “Advancements in the Science of Silicon Nanophotonics”
In 2012 I was a speaker at the ISSCC 10-40 Gb/s I/O Design Forum (“Optical vs. Electrical I/O: Reach, Bandwidth, Power Efficiency, Density and Cost”)
In 2011, 2012 and 2013 I was a short course instructor at OFC ("Circuits and Equalization Methods for Short Reach Optical Links")
Some recent and selected publications:
M. Ferriss, A. Rylyakov, H. Ainspan, J. Tierno, D.Friedman, "A 28GHz hybrid PLL in 32nm SOI CMOS",Symposium on VLSI Circuits , June 2013.
B. G. Lee, A. V. Rylyakov, J. E. Proesel, C. W. Baks, R. Rimolo-Donadio, C. L. Schow, A. Ramaswamy, J. E. Roth, M. Jacob-Mitos, G. Fish, "60-Gb/s Receiver Employing Heterogeneously Integrated Silicon Waveguide Coupled Photodetector", CLEO post-deadline paper, June 2013
B. G. Lee, W. M. Green, A. V. Rylyakov, S. Assefa, M. H. Khater, T. Barwicz, C. Reinholm, E. Kiewra, S. M. Shank, C. L. Schow, Y. A. Vlasov, "Monolithically integrated photonic switches driven by digital CMOS", CLEO, June 2013
D. Kuchta, A. Rylyakov, C. Schow, J. Proesel, F. Doany, C. W. Baks, B. Hamel-Bissell, C. Kocot, L. Graham, R. Johnson, G. Landry, E. Shaw, A. MacInnes, J. Tatum, "A 56.1 Gb/s NRZ Modulated 850nm VCSEL-Based Optical Link", OFC , March 2013
J. Proesel, A. Rylyakov, C. Schow, "Optical receivers using DFE-IIR equalization", ISSCC, Feb 2013
A. V. Rylyakov, C. L. Schow, B. G. Lee, F. E. Doany, C. W. Baks, J. A. Kash,"Transmitter Predistortion for Simultaneous Improvements in Bit Rate, Sensitivity, Jitter, and Power Efficiency in 20 Gb/s CMOS-Driven VCSEL Links", Journal of Lightwave Technology 2012. (paper)
A. V. Rylyakov, C. L. Schow, J. E. Proesel, D. M. Kuchta, C. Baks, N. Y. Li, C. Xie, K. P. Jackson, "A 40-Gb/s, 850-nm, VCSEL-Based Full Optical Link", OFC 2012 (paper, slides)
A. V. Rylyakov, C. L. Schow, B. G. Lee, W. M. J. Green, S. Assefa, F. E. Doany, M. Yang, J. Van Campenhout, C. V. Jahnes, J. A. Kash, Y. A. Vlasov,"Silicon Photonic Switches Hybrid-Integrated With CMOS Drivers", Journal of Solid-State Circuits 2012. (paper)
J. Proesel, C. Schow, A. Rylyakov,"25Gb/s 3.6pJ/b and 15Gb/s 1.37pJ/b VCSEL-Based Optical Links in 90nm CMOS", ISSCC 2012 (paper, slides)
C. Schow, A. Rylyakov, B. Lee, F. Doany, C. Baks, R. John, J. Kash, "Transmitter Pre-Distortion for Simultaneous Improvements in Bit-Rate, Sensitivity, Jitter, and Power Efficiency in 20 Gb/s CMOS-driven VCSEL Links", OFC 2011 PDP (paper, slides )
A. Rylyakov, C. Schow, B. Lee, W. Green, J. Van Campenhout, M. Yang, F. Doany, S. Assefa, C. Jahnes, J. Kash, Y. Vlasov, "A 3.9ns 8.9mw 4x4 Silicon Photonic Switch Hybrid Integrated with CMOS Driver", ISSCC 2011 (paper, slides )
A. Rylyakov, C. Schow, J. Kash, "A new ultra-high sensitivity, low-power optical receiver based on a decision-feedback equalizer", OFC 2011 (paper, slides )
"A DPLL-based per Core Variable Frequency Clock Generator for an Eight-Core POWER7 Microprocessor", (with J. Tierno et. al.), VLSI 2010. (paper, slides )
"A compact 6 GHz to 12 GHz digital PLL with coupled dual-LC tank DCO", (with A. Goel et. al.), VLSI 2010. (paper, slides )
"Broadband Silicon Photonic Switch Integrated with CMOS Drive Electronics", (with B. Lee et. al.), CLEO 2010. (slides)
"Low-Power CMOS-Driven Transmitters and Receivers", (with B. Lee et. al.), CLEO 2010. (slides)
"A 24-Channel 300 Gb/s 8.2 pJ/bit Full-Duplex Fiber-Coupled Optical Transceiver Module Based on a Single “Holey” CMOS IC", (with C. Schow et. al.), OFC 2010. (slides)
"A 7.5-GS/s 3.8-ENOB 52-mW Flash ADC with Clock Duty Cycle Control in 65nm CMOS", (with H. Chung et. al.), VLSI 2009. (slides)
"A 19Gb/s 38mW 1-Tap Speculative DFE Receiver in 90nm CMOS", (with D. Turker et. al.), VLSI 2009. (slides)
"Bang-Bang Digital PLLs at 11 GHz and 20 GHz with sub-200-fs Integrated Jitter for High Speed Serial Communication Applications", (with J. Tierno et. al.), ISSCC 2009. (slides)
"A 136-GHz Dynamic Divider in SiGe Technology", (with E. Laskin), SiRF 2009 (slides)
"A 90-Gb/s 2:1 Multiplexer with 1-Tap FFE in SiGe Technology", (with E. Laskin), CSICS 2008 (slides)
"A Wide Tuning Range (1 GHz-to-15 GHz) Fractional-N All-Digital PLL in 45nm SOI", (with J. Tierno et. al.), CICC 2008. (slides)
"A Modular All Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS", (with J. Tierno et. al.), ISSCC 2008 (slides)
"Low-power 16 x 10 Gb/s Bi-Directional Single Chip CMOS Optical Transceivers operating at < 5 mW/Gb/s/link", (with C. Schow et. al.), ISSCC, JSSC 2008
"An 11 Gb/s 2.4 mW Half-Rate Sampling 2-Tap DFE Receiver in 65nm CMOS", VLSI Symposium 2007 (slides)
"A Wide Power Supply Range (0.5V—1.3V) Wide Tuning Range (500 MHz—8 GHz) All Static CMOS All Digital PLL in 65 nm SOI,” (with J. Tierno et. al.) ISSCC 2007, JSSCC 2008 (slides)
"A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver with a 2-Tap DFE Using Soft Decision” (with K.L.J. Wong and C.K.K. Yang), VLSI Symposium 2006, JSSC 2007. Best student paper award. (slides)
"A Low Power 10Gb/s Serial Link Transmitter in 90nm CMOS" (with S. Rylov), CSICS 2005 (slides)
"A 10Gb/s Eye Opening Monitor in 0.13um CMOS" (with B. Analui et al.), ISSCC, JSSC 2005 (slides)
"96GHz Static Frequency Divider in SiGe Bipolar Technology" (with T. Zwick), JSSC 2004 (slides)
"A 30Gb/s 1:4 demultiplexer in 0.12um CMOS" (with S.Rylov et al.), ISSCC 2003 (slides)
"A 0.18um SiGe BiCMOS Reciever and Transmitter Chipset for SONET OC-768" (with M. Meghelli et al.), ISSCC, JSSC 2003 (slides)
"100GHz dynamic frequency divider in SiGe bipolar technology" (with L. Klapproth et al.), Electronics Letters 2003.
"50Gb/s SiGe BiCMOS 4:1 multiplexer and 1:4 demultiplexer for serial communication systems" (with M. Meghelli et al.), ISSCC, JSSC 2002 (slides)
"A 1.3 GSample/s 10-tap full-rate variable latency self-timed FIR with clocked interfaces" (with J. Tierno et al.), ISSCC 2002.
"A 2.3 GSample/s 10-tap digital FIR filter for magnetic recording read channels" (with S.Rylov et al.), ISSCC 2001.
"Rapid single flux quantum T-flip flop operating up to 770GHz" (with W. Chen et al.), Applied Superconductivity 1999. (paper)
"A fully integrated 16-channel RSFQ autocorrelator operating at 11GHz" (with D. Schneider and Yu. Polyakov), Applied Superconductivity 1999. (paper)
"Pulse jitter and timing errors in RSFQ circuits" (with K. Likharev), Applied Superconductivity 1999. (paper)
"Temperature dependence of the penetration depth of a field into a superconductor" (with G. Klimovitch and G. Eliashberg), JETP Letters 1991. (paper)
"Relaxation time of order parameter in YBaCuO single crystal" (with G. Leviev and M. Trunin), JETP Letters 1989. (paper)