Jinjun Xiong  Jinjun Xiong photo       

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Smarter Energy, Design Automation
Thomas J. Watson Research Center, Yorktown Heights, NY USA
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Professional Associations:  IEEE Member

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Introduction

My research interest is in the area of design automation for integrated circuits and systems. Recently I am working on statistical static timing analysis and its application to at-speed testing. For more details about my research, please see my Publications rap-sheet.

My research has won two Best Paper Awards and numerous Best Paper Award Nominations, including three nominations at ICCAD, one nomination at DAC, and one nomination at ASP-DAC. My research was also featured in EE Times in an article, titled "Hope seen for taming IC process variability at next design node" by Richard Goering. For details, please see the Honors webpage.

I obtained my Ph.D. degree in Electrical Engineering from UCLA in 2006, honored with the Outstanding Ph.D. Student Award for the class of 2006. You can find details about my education background through my Education webpage.

I have worked extensively in both academia and industry. Please see my past working Experience webpage for details.

Honors

Best Paper Awards

  1. Robust Extraction of Spatial Correlation, ACM International Symposium on Physical Design, 2006
  2. Performance Optimization Global Routing with RLC Crosstalk Constraints, International Conference on Application Specific Integrated Circuits and System-on-Chips, 2003

Best Paper Award Nominations

  1. Statistical Multilayer Process Space Coverage for At-Speed Test, ACM/IEEE the 46th Design Automation Conference, July 2009.
  2. Stochastic Current Prediction Enabled Frequency Actuator for Runtime Resonance Noise Reduction, ACM/IEEE the 14th Asia and South Pacific Design Automation Conference, January 2009.
  3. Statistical Path Selection for At-Speed Test, ACM/IEEE International Conference on Computer Aided Design, San Jose, California, November 2008.
  4. Compact Modeling of Variational Waveforms, ACM/IEEE International Conference on Computer Aided Design, San Jose, California, November 2007.
  5. Efficient Decoupling Capacitance Budgeting Considering Current Correlation Including Process Variation, ACM/IEEE International Conference on Computer Aided Design, San Jose, California, November 2007.

IBM Awards

  1. IBM Research Division Award for EinsStat IP Revenue, IBM T.J. Watson Research Center, July 2007.
  2. IBM Second Plateau Invention Achievement Award, IBM T.J. Watson Research Center, December 2008.
  3. IBM First Plateau Invention Achievement Award, IBM T.J. Watson Research Center, June 2007.
  4. IBM First to Ninth Invention Achievement Awards, 2006-present.

Distinguished Graduate Fellowship

  1. University of California, Los Angeles, 2002
  2. University of Wisconsin, Madison, 2001
  3. Tsinghua University, China, 1998,1999

Distinguished Under-Graduate Fellowship

  1. Tsinghua University, China, 1994, 1995, 1996,1997

Beijing Science and Technology Award

  1. Bronze Medal, the Government of Beijing, China, 2002

Education

Ph.D., Electrical Engineering, University of California, Los Angeles, May 2006

Thesis: Modelign and Design Optimization Considering Nanometer Process Variation Effects

Outstanding Ph.D. Award

M.S., Electrical and Computer Engineering, University of Wisconsin, Madison, August 2002

Thesis: Full-chip Routing Optimization with RLC Crosstalk Budgeting

M.E., Precision Instruments and Control, Tsinghua University

Thesis: Design of an Eight Terabyte Storage System: Concept and Implementation, August 2000

B.E., Precision Instruments and Control, Tsinghua University, August 1998

Thesis: Implementation of an Embedded Control System for Storage Tower

Outstanding B.E. Award

B.E., Industrial Engineering, Tsinghua University, August 1998

Thesis: An Ergonomic-aware Human Machine Interaction System Design

Experience

Research Staff Member, IBM Thomas J. Watson Research Center, Yorktown, NY, July 2006 - Present

Design automation for integrated circuits and systems.

Research Co-op, IBM Thomas J. Watson Research Center, Yorktown, NY, June 2005 - December 2005

Worked on statistical timing analysis and statistical circuit optimization. One of the key developers of EinsStat, IBM's flagship statistical timer. Also worked on PDS, IBM's flagship physical synthesis tool.

Research Co-op, Rio Design Automation, Inc., Santa Clara, CA, April 2004 - October 2004

Proposed a chip-package co-design flow. Developed an RLC extraction methodology for redistribution layer routing and package traces. Developed a novel algorithm for chip-package co-placement engine.

Technical Consultant, ULSITech Corporation, San Jose, CA, September 2004 - December 2004

Provided technical consultant on capacitance extraction techniques considering accuracy and speed-up issues.

Technical Consultant, Rio Design Automation, Inc., Santa Clara, CA, October 2004 - June 2005

Provided technical consultant on issues like I/O planning, signal integrity, power integrity, escape routing, package power plane modeling, and chip-package co-placement.

Research Assistant, Electronic Design Automation Lab, University of California, Los Angeles, August 2002 - June 2006

Worked on techniques for interconnect modeling and design, physical design, low-power system design, and chip-package co-design. Research involved extraction, modeling, signal integrity, power integrity, statistical timing analysis, design for variability, and design for manufacturing.

Research Assistant, Electronic Design Automation Lab, University of Wisconsin, Madison, August 2001 - August 2002

Worked on interconnect modeling and design considering signal and power integrity constraints.

Research Assistant, Biomechanics & Ergonomics Lab, University of Illinois, Urbana-Champaign, Research Assistant, August 2000 - August 2001

Worked on biomechanics and ergonomics. Proposed a novel human lumbar kinematics model. Developed a human motion analysis package based on in-vivo motion measurement and sensing.

Research Intern, Tsinghua Tongfang Corporation, Beijing, China, Summers in 1997 - 2000

Developed the firmware for an embedded storage system. Implemented a real-time operating system for a one-to-fifteen-copy CD/DVD duplicator system. Designed an EIDE-to-SCSI protocol bridge card.

Research Assistant, Optical Memory National Engineering Research Center, Tsinghua University, China, August 1997 - August 2000

Worked on embedded and real-time system designs. Proposed a novel file system for terabyte- scale storage systems. Developed a prototype storage system with eight terabyte capacity. Implemented the whole embedded firmware system with all electrical-mechanical controlling sub-systems for an auto-CD/DVD media changer system. Filed four China patents.

Publications

Patents

  1. J. Pei, Y. Xiao, J. Xiong , Seamless Integration of Multiple Storage Systems under One Target, China Patent, CN 1094217C, issued on November 13, 2002.
  2. J. Pei, J. Xiong , Y. Li, L. Pan, Architecture and Implementation of a Plug-and-play High-capacity Virtual Compact Disc Storage System China Patent, CN 1118758C, issued on August 20, 2003
  3. J. Xiong , J. Pei, An Extendable High-capacity Virtual Compact Disc File System: Construction Algorithms and Hardware Implementation, China Patent, CN 1137441C, issued on February 4, 2004.
  4. J. Pei, J. Xiong , Y. Xiao, A Multiple-driver-connected Compact Disc Library System under Single SCSI Logic Unit, filed with the China Patent Office, CN 1263310A, August 2000.
  5. N. Venkateswaran, C. Visweswariah, J. Xiong , V. Zolotov, System and Method of Criticality Prediction in Statistical Timing Analysis, filed with the U.S. Patent Office, December 16, 2005. Issued US 7437697 on October 14, 2008.
  6. C. Visweswariah, J. Xiong , V. Zolotov, System and Method for Optimization of a Digital Integrated Circuit with Yield Considerations, Docket YOR-9-2005-0500US1, filed with the U.S. Patent Office, December 2005
  7. E. A. Foreman, G. D. Grise, P. A. Habitz, V. Iyengar, D. E. Lackey, C. Visweswariah, J. Xiong , V. Zolotov, IC Chip At-functional-speed Testing with Process Coverage Evaluation, Docket BUR-9-2006-0235US1, filed with the U.S. Patent Office, April 2007.
  8. S. Abbaspour, D. J. Hathaway, C. Visweswariah, J. Xiong , V. Zolotov, Representing and Propagating a Variational Voltage Waveform in Statistical Static Timing Analysis of Digital Circuits, Docket YOR-9-2006-0597US1, filed with the U.S. Patent Office, April 2007.
  9. C. Visweswariah, J. Xiong and V. Zolotov, System and method for incremental criticality and yield gradient computation, Docket YOR-9-2007-0347US1, filed with the U.S. Patent Office, October 2007.
  10. C. Visweswariah, J. Xiong and V. Zolotov, Method and apparatus for computing test margins for at-speed testing, Docekt YOR-9-2007-0614-US1, filed with the U.S. Patent Office, January 14, 2008.
  11. H. Fatemi, C. Visweswariah, J. Xiong and V. Zolotov, Method and apparatus for statistical path selection for at-speed testing, Disclosure YOR-9-2007-0613-US1, filed
  12. V. Iyengar, D. Lackey, S. Venkatesan, C. Visweswariah and J. Xiong , Critical path selection for at-speed test, Disclosure BUR-9-2007-0146US1, filed
  13. D. Sinha, N. Venkateswaran, C. Visweswariah, J. Xiong , V. Zolotov , Reversible Statistical Maximum and Minimum Operations for Efficient Incremental Statistical Timing Analysis and Optimization, YOR820080279, May 13, 2008.
  14. Y. Shi, C. Visweswariah, J. Xiong , V. Zolotov, System and Method for Multilayer Process Space Coverage and Path Selection for At-speed Testing, YOR820080853, August 12, 2008
  15. C. Visweswariah, J. Xiong , V. Zolotov, System and Method for Variation-aware Test Pattern Generation, YOR820081136, October 14, 2008

Book

  1. J. Xiong , Mastering Flash 4, Illustrated, in Chinese, China Electricity Power Press, Beijing, China, ISBN: 7-5083-0303-2, 2000.

Journals

  1. X. Zhang, J. Xiong , Model-guided derivation of lumbar vertebral kinematics in vivo reveals the difference between external marker-defined and internal segmental rotations, Journal of Biomechanics, Vol. 36, No. 1, January 2003, pp 9-17.
  2. X. Zhang, J. Xiong , A. Bishop, The effects of load and speed on lumbar vertebral kinematics during lifting motions, Human Factors, Vol. 45, No. 2, 2003, pp 296-306.
  3. J. Xiong , L. He, Full-chip Routing Optimization with RLC Crosstalk Budgeting, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, No. 3 , March 2004, pp 366-377.
  4. L. Zhang, T. Jing, X. Hong, J. Xu, J. Xiong , L. He, CEE-Gr: A Global Router with Performance Optimization under Multi-Constraints, Chinese Journal of Semiconductors, Vol. 25, No. 5, 2004, pp 508-515.
  5. J. Xiong , L. He, Extended Global Routing with RLC Crosstalk Constraints, IEEE Transactions on Very Large Scale Integration Systems, Vol. 13, No. 3, March 2005, pp 319-329.
  6. J. Xiong , L. He, Full-chip Multilevel Routing for Power and Signal Integrity, Integration - the VLSI journal, Vol. 40, 2007, pp 226-234.
  7. L. He, A. Kahng, K. Tam, J. Xiong , Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No.4, May 2007.
  8. J. Xiong , V. Zolotov, L. He, Robust Extraction of Spatial Correlation, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 4, April 2007.
  9. J. Xiong , L. He, Probabilistic Transitive-closure Ordering and its Application on Variational Buffer insertion, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 4, April 2007, pp 739-742.
  10. Z. Cao, T. Jing, J. Xiong , Y. Hu, L. He, and X. Hong, Fashion: A Fast and Accurate Solution to Global Routing Problem,, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 4, April 2008, pp.726-737.
  11. Y. Shi, J. Xiong , C. Liu, and L. He, Efficient Decoupling Capacitance Budgeting Considering Operationand Process Variations, IEEE Transactions on Computer-Aided esign of Integrated Circuits and Systems, accepted.
  12. L. Cheng, J. Xiong , and L. He, Non-Gaussian Statistical Timing Analysis Using Second-Order Polynomial Fitting, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, accepted.

Conference Papers

  1. J. Xiong , L. Pan, J. Pei, D. Meng, Eight-terabyte storage system by a new file system, International Society for Optical Engineering Symposium (SPIE) on Optical Storage, Vol. 4085, 2000.
  2. X. Zhang, J. Xiong, A. Bishop, Vertebral Kinematic Description Based on In-Vivo Measurement of Surface Marker Motions, The 25th American Society of Biomechanics Annual Meeting, 2001.
  3. X. Zhang, J. Xiong, A. Bishop, The effects of load and speed on vertebral kinematics during lifting motions, The 45th Human Factors and Ergonomics Society Annual Meeting, 2001.
  4. J. Xiong, J. Chen, J. Ma, L. He, Post Global Routing RLC Crosstalk Budgeting, ACM International Conference on Computer-Aided Design, San Jose, November 2002.
  5. L. Zhang, T. Jing, X. Hong, J. Xu, J. Xiong, L. He, Performance optimization global routing with RLC crosstalk constraints, International Conference on ASIC, Vol. 1, October 2003. Best Student Paper Award
  6. J. Xiong, L. He, Full-chip Multilevel Routing for Power and Signal Integrity, International Conference on Design, Automation and Test in Europe, Paris, France, Feburary 2004.
  7. C. Long, J. Xiong, L. He, On Optimal Physical Synthesis of Sleep Transistors, ACM International Symposium on Physical Design, Tucson, Arizona, March 2004.
  8. L. Zhang, T. Jing, X. Hong, J. Xiong, L. He, Performance and RLC Crosstalk Driven Global Routing, International Symposium on Circuits and Systems, Vol.5, May 2004.
  9. X. Zhao, Y. Cai, Q. Zhou, X. Hong, L. He, J. Xiong, Shielding Area Optimization under the Solution of Interconnect Crosstalk, International Symposium on Circuits and Systems, Vol. 5, May 2004.
  10. L. He, A. Kahng., K. Tam, J. Xiong, Variability-Driven Considerations in the Design of Integrated-Circuit Global Interconnects, IEEE VLSI Multilevel Interconnection Conference, October 2004. (Invited Paper)
  11. J. Xiong, L. He, Probabilistic Congestion Model Considering Shielding for Crosstalk Reduction , IEEE/ACM Asia South Pacific Design Automation Conference, January 2005.
  12. T. Jing, L. Zhang, J. Liang, J. Xu, X. Hong, J. Xiong, L. He, A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem, IEEE/ACM Asia South Pacific Design Automation Conference, January 2005.
  13. L. He, A. Kahng, K. Tam, J. Xiong, Design of IC Interconnects with Accurate Modeling of CMP, International Society for Optical Engineering Symposium (SPIE) on Microlithography, Feburary 2005.
  14. J. Xiong, K. Tam, L. He, Buffer insertion considering process variation, Design Automation and Test in Europe, Munich, Germany, March 2005.
  15. L. He, A. Kahng, K. Tam, J. Xiong, Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation, ACM International Symposium on Physical Design, April 2005.
  16. J. Liang, T. Jing, X. Hong, J. Xiong, L. He, Power/Ground Network Aware and Row-Based Solutions to the Crosstalk Driven Routing Problem, International Conference on Application Specific Integrated Circuits, October 2005.
  17. J. Xiong, Y. Wong, E. Sarto, L. He, Constraint Driven I/O Planning and Placement for Chip-package Co-design, IEEE/ACM Asia South Pacific Design Automation Conference, January 2006.
  18. J. Xiong, L. He, Fast Buffer Insertion Considering Process Variations, ACM International Symposium on Physical Design, San Jose, California, April 2006.
  19. J. Xiong, V. Zolotov, L. He, Robust Extraction of Spatial Correlation, ACM International Symposium on Physical Design, San Jose, California, April 2006. Best Paper Award
  20. J. Xiong, V. Zolotov, N. Venkateswaran, C. Visweswariah, Criticality Computation in Parameterized Statistical Timing, IEEE/ACM Design Automation Conference, July 2006.
  21. L. Cheng, J. Xiong, L. He, FPGA Performance Optimization via Chipwise Placement Considering Process Variations, International Conference on Field Programmable Logic and Applications, August 2006.
  22. Z. Cao, T. Jing, J. Xiong, Y. Hu, L. He, and X. Hong, DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm, IEEE/ACM Asia South Pacific Design Automation Conference, January 2007.
  23. R. Chen, E. A. Foreman,P. A. Habitz, J. G. Hemmett, K. Kalafala, J. S. Piaget, P. Qi, N. Venkateswaran, C. Visweswariah, J. Xiong, and V. Zolotov, Static Timing: Back to Our Roots, ACM/IEEE International Workshop on Timing Issues , Austin, TX, February 2007.
  24. L. Cheng, J. Xiong and L. He, Non-Linear Statistical Static Timing Analysis for Non-Gaussian Variation Sources, IEEE/ACM Design Automation Conference, June 2007.
  25. V. Zolotov, J. Xiong, S. Abbaspour, D. J. Hathaway and C. Visweswariah, Compact Modeling of Variational Waveforms, ACM International Conference on Computer-Aided Design, San Jose, November 2007. Best Paper Award Nomination
  26. V. Iyengar, J. Xiong, S. Venkatesan, V. Zolotov, D. Lackey, P. Habitz, C. Visweswariah, Variation-Aware Performance Verification Using At-Speed Structural Test And Statistical Timing, ACM International Conference on Computer-Aided Design, San Jose, November 2007.
  27. Y. Shi, J. Xiong, C. Liu and L. He, Efficient Decoupling Capacitance Budgeting Considering Current Correlation Including Process Variation, ACM International Conference on Computer-Aided Design, San Jose, November 2007, Best Paper Award Nomination
  28. L. Cheng, J. Xiong and L. He, NonGaussian Statistical Timing Analysis Using Second Order Polynomial Fitting, IEEE/ACM Asia South Pacific Design Automation Conference, January 2008.
  29. R. Chen, L. Zhang, V. Zolotov, C. Visweswariah, and J. Xiong, Static Timing: Back to Our Roots, IEEE/ACM Asia South Pacific Design Automation Conference, January 2008.
  30. J. Xiong, V. Zolotov, and C. Visweswariah, Incremental criticality and yield gradients, International Conference on Design, Automation and Test in Europe, Munich, Germany, March 2008.
  31. J. Xiong, V. Zolotov, C. Visweswariah, and P. A. Habitz, Optimal margin computation for at-speed test, International Conference on Design, Automation and Test in Europe, Munich, Germany, March 2008.
  32. W. Zhang, W. Yu, Z. Wang, Z. Yu, R. Jiang, and J. Xiong, An Efficient Method for Chip-Level Statistical Capacitance Extraction Considering Process Variations with Spatial Correlation, International Conference on Design, Automation and Test in Europe, Munich, Germany, March 2008.
  33. V. Zolotov, J. Xiong, H. Fatemi, and C. Visweswariah, Statistical Path Selection for At-speed Testing, ACM International Conference on Computer-Aided Design, San Jose, November 2008. Best Paper Award Nomination
  34. Y. Shi, J. Xiong, H. Chen, and L. He, Stochastic Current Prediction Enabled Frequency Actuator for Runtime Resonance Noise Reduction, IEEE/ACM Asia South Pacific Design Automation Conference, January 2009. Best Paper Award Nomination
  35. Y. Shi, W. Yao, J. Xiong, and L. He, Incremental and On-demand Random Walk for Iterative Power Distribution Network Analysis, IEEE/ACM Asia South Pacific Design Automation Conference, January 2009.