Pouya Hashemi  Pouya Hashemi photo       

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Research Staff Member, CMOS Exploratory Devices and Integration
Thomas J. Watson Research Center, Yorktown Heights, NY USA


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More information:  Citation  |  My MIT Webpage


Pouya Hashemi received his Ph.D. degree (with honor) in Department of Electrical Engineering and Computer Science at Massachusetts Institute of Technology (MIT) in September 2010 and his B.Sc. and M.Sc. degrees in electrical engineering, both with highest honors, from University of Tehran in 2003 and 2005, respectively. 

He is currently a research staff member (RSM) and device integration team lead at IBM research center at Yorktown Heights, NY, focusing on exploratory CMOS devices and integration for sub-10nm nodes. In 2010 and 2011, he was a post-doctoral associate at the MIT Microsystems Technology Laboratories working on advanced strained-Ge on insulator substrates and top-down fabricated Si/Ge nanowires for high-performance CMOS and SiGe based solar cells. From 2002 to 2005, he was with the Thin-Film Research Laboratories at University of Tehran working on electrical and optical properties of nano-crystalline silicon and fabrication of low temperature silicon and germanium thin-film transistors on flexible substrates. In 2005, he joined MIT Microsystems Technology Laboratories where his research was focused on fabrication and investigation of carrier transport in nano-scale strained SOI, silicon-germanium and germanium channel CMOS devices with planar and nanowire architectures. In summer 2009, he was with IBM T.J. Watson photovoltaic research center at Yorktown Heights, NY where he worked on process development of multi-crystalline based Si solar cells.

Dr. Hashemi is the recipient of the 2014 IEEE George E. Smith award in 2015, IBM Ph.D. Fellowship award in 2008, TSMC outstanding research award/commendation in 2010, the Jin-Au Kong Award (Honorable Mention) for best MIT Electrical Engineering Ph.D. Thesis in 2011, and winner of the MIT Microsystems Technology Laboratories Doctoral Dissertation Seminar in Spring 2011. His cutting-edge research on strained SiGe FinFETs at IBM has selected for three times in a row as the symposium highlight paper at the VLSI Technology Symposia, a main forum for reporting technological breakthrough in semiconductors and integrated circuits. In addition, his work has led to over 90 publications in peer-reviewed journals and prestigeous conferences, including IEEE IEDM, VLSI Technology Symposia, EDL, TED, Nano Lett., etc and over 200 pending or issued US patents. He is titled IBM Master Inventor since 2015 and is also a Senior Member of IEEE Electron Device Society (EDS).