Chandu Visweswariah  Chandu Visweswariah photo       

contact information

IBM Fellow, Smarter Energy and Environmental Science; Director, Smarter Energy Research Institute (SERI)
Thomas J. Watson Research Center, Yorktown Heights, NY USA
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Professional Associations

Professional Associations:  IEEE Circuits and System Society

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Name Chandu Visweswariah
Position IBM Fellow, Smarter Energy and Environmental Science; Director, Smarter Energy Research Institute (SERI)
Department Industry Solutions Research, IBM Thomas J. Watson Research Center
Research Interests Smarter energy, weather modeling, natural resources, sustainability, big data, analytics, optimization techniques, circuit simulation, microelectronic device modeling, circuit optimization, static timing, statistical timing analysis, VLSI design, library characterization, chip timing methodology, CAD tools/Design Automation and novel devices.
Contact Information IBM Thomas J. Watson Research Center 1101 Kitchawan Road, Route 134
Office 10-130
Yorktown Heights, NY 10598, U.S.A.
Voice: 914-945-1164, IBM tieline 862-1164
Home: 914-271-6118
Cell: 202-253-3972
FAX: 914-945-4184, IBM tieline 862-4184
Email: chandu@us.ibm.com

Contents

Education

Ph.D. Electrical and Computer Engineering Carnegie Mellon University 1989
M.S. Electrical and Computer Engineering Carnegie Mellon University 1986
B.Tech. Electrical Engineering Indian Institute of Technology (Chennai) 1985

Employment

9/2013-present IBM Fellow and Senior Manager, Smarter Energy and Environmental Science IBM Thomas J. Watson Research Center
4/2013-9/2013 IBM Fellow and Senior Manager, Timing and Circuit Analysis Electronic Design Automation, IBM Systems and Technology Group
5/2009-3/2013 Distinguished Engineer and Senior Manager, Timing and Circuit Analysis Electronic Design Automation, IBM Systems and Technology Group
5/2004-5/2009 Manager, Circuit and Interconnect Analysis IBM Thomas J. Watson Research Center
9/1989-5/2009 Research Staff Member IBM Thomas J. Watson Research Center

Honors and awards

  • 2016 A. Richard Newton Technical Impact Award in Electronic Design Automation for the paper C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker and S. Narayan, "First-order incremental block-based statistical timing analysis," published in the Design Automation Conference 2004. The award is jointly sponsored by the IEEE Council on EDA and the ACM Special Interest Group on Design Automation. The award honors a person or persons for an outstanding technical contribution within the scope of electronic design automation, as evidenced by a paper published at least ten years before the presentation of the award.
  • IBM Twenty Fourth Plateau Invention Achievement Award, January 2016.
  • Distinguished Alumnus Award from the Indian Institute of Technology, Madras, India, 2016.
  • IBM Twenty Third Plateau Invention Achievement Award, August 2015.
  • IBM Twenty Second Plateau Invention Achievement Award, March 2015.
  • IBM Twenty First Plateau Invention Achievement Award, June 2014.
  • IBM Twentieth Plateau Invention Achievement Award, January 2014.
  • Design Automation Conference (DAC) Top 10 Cited Paper: award for being among the top 10 DAC papers by citation across 50 years of DAC, awarded at the 50th DAC in Austin, TX, June 2013, for the paper:
    First-order incremental block-based statistical timing analysis.
    C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, and S. Narayan.
    Design Automation Conference (DAC), San Diego, CA, pages 331--336, June 2004.
  • Appointed IBM Fellow, April 2013. Citation reads as follows: "Chandu Visweswariah is a pioneer in circuit analysis and optimization, as well as the inventor of statistical timing. He has developed techniques used in every IBM chip design, including formal circuit tuning and gate-level timing sign-off. These fundamental contributions have improved performance, ensured timing correctness, combated variability and enhanced design productivity across three generations of IBM's fastest microprocessors and most complex ASICs. Chandu is a widely recognized industry leader with 68 patents, more than 100 publications and numerous awards including Electronic Design News' Innovator of the Year."
  • IBM Nineteenth Plateau Invention Achievement Award, November 2012.
  • IBM Eighteenth Plateau Invention Achievement Award, October 2012.
  • Selected for "Best of IBM," May 2012.
  • IBM Corporate Award for "Statistical Timing Analysis of Integrated Circuits," May 2012.
  • IBM Seventeenth Plateau Invention Achievement Award, January 2012.
  • IBM Sixteenth Plateau Invention Achievement Award, August 2011.
  • Appointed IBM Master Inventor, January 2011.
  • IBM Fifteenth Plateau Invention Achievement Award, November 2010.
  • IBM Fourteenth Plateau Invention Achievement Award, April 2010.
  • IBM High Value Patent Award for U. S. Patent 7,620,921 IC chip at-functional-speed testing with process coverage evaluation, November 2009.
  • IBM Thirteenth Plateau Invention Achievement Award, September 2009.
  • IBM High Value Patent Award for U. S. Patent 7,555,740 Method and system of evaluating statistical sensitivity credit in path-based hybrid multi-corner static timing analysis, August 2009.
  • Inducted into the IBM Academy of Technology, June 2009.
  • IBM Twelfth Plateau Invention Achievement Award, April 2009.
  • Appointed IBM Distinguished Engineer, May 2009.
  • IBM Eleventh Plateau Invention Achievement Award, July 2008.
  • IBM Tenth Plateau Invention Achievement Award, April 2008.
  • IBM Ninth Plateau Invention Achievement Award, March 2008.
  • IBM Research Division Outstanding Accomplishment for the EinsStat project, January 2008.
  • Supplemental Patent Issue Award for U. S. Patent 7,117,466 System and method for correlated process pessimism removal for static timing analysis awarded to "the inventors of the top 10% of IBM United States patents that issued during the 2006 calendar year."
  • Supplemental Patent Issue Award for U. S. Patent 7,093,208 Method for tuning a digital design for synthesized random logic circuit macros in a continuous design space with optional insertion of multiple threshold voltage devices awarded to "the inventors of the top 10% of IBM United States patents that issued during the 2006 calendar year."
  • IBM Eighth Plateau Invention Achievement Award, November 2007.
  • IBM Outstanding Innovation Award for "EinsStat (Statistical Timing Tool) IP Revenue," July 2007.
  • IBM Seventh Plateau Invention Achievement Award, April 2007.
  • IBM Sixth Plateau Invention Achievement Award, February 2007.
  • IBM Research Division Accomplishment for the EinsStat project, January 2007.
  • The EinsTimer Statistical Timing development team won the EDN (Electronic Design News) Innovator of the Year award, April 2006.
  • EinsTimer Statistical Timing won the EDN (Electronic Design News) Innovation of the Year award in the EDA (Design and Implementation) category, April 2006.
  • IBM Fifth Plateau Invention Achievement Award, December 2005.
  • Selected for the December 2005 EE Times "Great Minds, Great Ideas Project" and special issue. Chandu Visweswariah. He's getting the chips to run on time.
  • Supplemental Patent Issue Award for U. S. Patent 6,826,733 Parameter variation tolerant method for circuit design optimization awarded to "the inventors of the most valuable IBM United States patents that issued during the 2004 calendar year."
  • 2004 Pat Goldberg Memorial IBM Research Best Paper Award in Computer Science, Electrical Engineering and Mathematics for the paper:
    First-order incremental block-based statistical timing analysis.
    C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, and S. Narayan.
    Design Automation Conference (DAC), San Diego, CA, pages 331--336, June 2004.
  • Elected Fellow of the Institute of Electrical and Electronics Engineers (IEEE) for "contributions to large-scale integrated circuits," effective January, 2005.
  • Best paper in the "Back-end design" category, Design Automation Conference (DAC) 2004, San Diego, CA, for the paper:
    First-order incremental block-based statistical timing analysis.
    C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, and S. Narayan.
    Design Automation Conference (DAC), San Diego, CA, pages 331--336, June 2004.
  • 2003 Pat Goldberg Memorial IBM Research Best Paper Award in Computer Science, Electrical Engineering and Mathematics for the paper:
    Statistical timing for parametric yield prediction of digital integrated circuits.
    J. A. G. Jess, K. Kalafala, S. R. Naidu, R. H. J. M. Otten, and C. Visweswariah.
    Design Automation Conference (DAC), Anaheim, CA, pages 932--937, June 2003.
  • IBM Fourth Plateau Invention Achievement Award, May 2004.
  • IBM Third Plateau Invention Achievement Award, September 2003.
  • IBM Corporate Award for "Formal Static Circuit Tuning Tool," June 2003.
  • IBM Second Plateau Invention Achievement Award, May 2003.
  • The following two papers were selected for the "Best of ICCAD" 2002 volume of 40 of the best papers published during 20 years of the International Conference on Computer-Aided Design (ICCAD):
    • C. Visweswariah and R. A. Rohrer, SPECS2: an integrated circuit timing simulator, ICCAD 1987.
    • A. R. Conn, P. K. Coulman, R. A. Haring, G. L. Morrill, and C. Visweswariah, Optimization of custom MOS circuits by transistor sizing, ICCAD 1996.
  • Second place, "Best mandatory course 2001/2002," Department of Electrical Engineering, Eindhoven University of Technology, Eindhoven, The Netherlands, for teaching "Ontwerptechnologie 5L050" (Design Technology), summer 2002.
  • IBM First Plateau Invention Achievement Award, June 2002.
  • IBM Outstanding Technical Achievement Award for "Invention and development of EinsTuner," December 2001.
  • IBM Execute Now Award for "Design and implementation of the Freeway (G7) microprocessor," July 2001.
  • IBM Research Division Accomplishment for the EinsTuner project, January 2001.
  • IBM Research Division Award for "Expedited release of production EinsTuner," September 2000.
  • Contributions to the INFORMS prize, which was awarded to IBM by the Institute for Operations Research and the Management Sciences, November 1999.
  • IBM Research Division Award for "Design and realization of the Alliance (G5) microprocessor," November 1998.
  • IBM Research Division Award for "Contributions to the design and realization of the Alliance (G4) microprocessor," November 1997.
  • IBM First Patent Application Invention Achievement Award, June 1997.
  • IBM Research Division Accomplishment for the JiffyTune project, January 1997.
  • IBM Quarterly Highlight project of the Computer-Aided Design and Verification department for the JiffyTune project, fourth quarter, 1996.
  • IBM Blue Chip Award, May 1996.
  • Senior Member, Institute of Electical and Electronics Engineers (IEEE), September 1995.
  • IBM Research Division Technical Group Award for "Contributions to the Alliance first RIT and stand alone bring-up," December 1995.
  • Coauthor, McGraw Hill "Book of the Month," April 1995.
  • IBM Outstanding Technical Achievement Award for "Simulation Program for Electronic Circuits and Systems (SPECS)," May 1994.
  • Fellowship from AT&T Bell Laboratories for the duration of doctoral studies at Carnegie Mellon University.
  • Best Paper in Session, SRC Techcon, October 1988.
  • Research Assistantship from Carnegie Mellon University for the duration of Master's and PhD studies in the Department of Electrical and Computer Engineering.
  • Best Paper and Presentation, IEEE All-India Students' Symposium on "Recent Trends in CAD," October 1984.
  • Deutscher Akademischer Austauschdienst (DAAD), West Germany: selected based on academic merit for a student exchange program to Germany, summer 1983.
  • Certificate of Academic Distinction, Indian Institute of Technology, Chennai, India, 1980 and 1981.

Professional activities

  • Fellow, IEEE; member, IEEE Circuits and Systems Society; member, IBM Academy of Technology; member, Union of Concerned Scientists.
  • Panelist, DistribuTECH "Integrating DER - How Are We Going to Make "From Anywhere, To Anywhere" Work in the Real World?," Orlando, February 2016.
  • Panelist, DistribuTECH "Grid 2025" Mega Panel, San Diego, February 2015.
  • Member, Solar Task Force, Town of Cortlandt, NY, 2014.
  • Panel chair, "EDA Court: Hierarchical Construction and Timing Sign-off of SoCs," ACM/IEEE international workshop on timing issues in the specification and synthesis of digital systems (TAU), Lake Tahoe, NV, March 2013.
  • Session chair, "Future technologies," ACM/IEEE international workshop on timing issues in the specification and synthesis of digital systems (TAU), Taipei, Taiwan, January 2012.
  • Member, "IBM Smarter ASIC Task Force," July 2011 to February 2012.
  • Member, User Track Best Paper Committee, Design Automation Conference (DAC), San Diego, CA, June 2011.
  • Selected for the IBM Executive Service Corps (ESC), September 2010. Volunteered to provide 3 weeks of consulting services to the City of Rio de Janeiro, Brazil, on various projects related to its preparations for the Soccer World Cup 2014 and Summer Olympics 2016. Advised City Hall on a Sustainability Master Plan to address the needs of the Olympics as well as the longer-term needs of the City of Rio.
  • Session chair, "Statistical techniques for silicon to model correlation," Design Automation Conference (DAC), Anaheim, CA, June 2010.
  • Panelist, "Statistical digital design: what does it take?," 4th IEEE International Workshop on Design for Manufacturability and Yield, Anaheim, CA, June 2010.
  • Session chair, "Chip level implementation," IBM EDA Education Week, May 2010.
  • Session chair, "Model order reduction techniques and applications," Design Automation Conference (DAC), San Francisco, CA, July 2009.
  • Panelist, "Process variation: the line blurs," IEEE North Atlantic Test Workshop (NATW), Hopewell Junction, NY, May 2009.
  • Panelist, Net Seminar moderated by Richard Goering, Senior Editor of EE Times, on "The Road to Nanometer CMOS," March 2006. The Net Seminar was part of EE Times' "Great Minds, Great Ideas" project.
  • Organizer, full-day tutorial, "Practical Aspects of Coping with Variability: An Electrical View" at the Design Automation Conference, San Francisco, CA, July 2006. Speakers were Dr. X-W. Lin, Director of R&D, Synopsys, Dr. B. Nikolic, Associate Professor, UC Berkeley, Dr. P. A. Habitz of IBM and Dr. R. Radojcic, Qualcomm.
  • Member, task force on "IBM value-add with silicon modeling and statistical timing," November 2005.
  • Member, PAC2 Technical Program Committee, The Second Watson Conference on Interaction between Architecture, Circuits and Compilers, September 2005.
  • Session chair and panel moderator, special session on "DFM and variability: theory and practice" at the 2005 Design Automation Conference (DAC), Anaheim, CA, June 2005.
  • Focus group discussion leader, "Statistical static timing analysis and optimization: sizzle or fizzle?," at the ACM/IEEE international workshop on timing issues in the specification and synthesis of digital systems (TAU), Austin, TX, February 2004.
  • Member, PhD committee of Srinath R. Naidu (advisor: Prof. Ralph H. J. M. Otten), Department of Electrical Engineering, Eindhoven University of Technology, The Netherlands, thesis "Tuning for yield: towards predictable deep sub-micron manufacturing," July, 2004.
  • Panel organizer, "Libraries: lifejacket or straitjacket?" at the Design Automation Conference (DAC), 2003.
  • Member, NSF panel to evaluate "Information Technology Research" proposals, April 2003.
  • Visiting assistant professor on sabbatical assignment, Department of Electrical Engineering, Eindhoven University of Technology, Eindhoven, The Netherlands, April to August 2002.
  • Technical Program Committee, Design Automation Conference (DAC), 2003, 2002 and 2001. Sub-committe chair for "Timing and simulation," 2002 and 2003.
  • Organizer, Circuits Education Session seminar series, East Fishkill, NY, 03/2000 to 03/2002.
  • Senior Member, IEEE; member, IEEE Circuits and Systems society.
  • Member, IBM "Futures" team to focus on information technology trends, June 1998.
  • Technical Program Committee, International Conference on Computer-Aided Design (ICCAD), 1998, 1997 and 1996.
  • Technical Program Committee, Custom Integrated Circuits Conference (CICC), 1996.
  • Member, PhD committee of Anirudh Devgan (advisor: Prof. Ronald A. Rohrer), Department of Electrical and Computer Engineering, Carnegie Mellon University, thesis "Adaptively controlled explicit simulation," November, 1993.
  • Member, PhD committee of Kimon Michaels (advisor: Prof. Andrzej Strojwas), Department of Electrical and Computer Engineering, Carnegie Mellon University, thesis "Variable accuracy device modeling for event-driven circuit simulation," March 1993.
  • Technical Program Committee, International Conference on Computer Design (ICCD), 1992.
  • Corporate Ph.D. recruiter at Carnegie Mellon University, 1992 - 1998.
  • Co-chair, IBM internal Circuit Tuning Workshop, 1995.
  • Member, CAD Framework Initiative (CFI) co-simulation and simulation backplane standards committee (1992-1993).
  • Session chair and session organizer of several sessions at the International Conference on Computer-Aided Design (ICCAD), Design Automation Conference (DAC), Custom Integrated Circuits Conference (CICC), International Conference on Computer Design (ICCD), and TAU (ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems) conferences over the years. See curriculum vitae for details.
  • Reviewer for IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Circuits and Systems, Design Automation Conference (DAC) and International Symposium on Circuits and Systems (ISCAS).

Significant projects

  • Senior manager, Smarter Energy and Environmental Science, since September 2013. Projects include Analytics and Optimization Management System (AOMS), a platform for applying analytics and optimization to run electric utilities more efficiently; Deep Thunder, a weather modeling system; and Jefferson, a study of the contaminants in Lake George and deleterious effects thereof.
  • Senior manager, timing and circuit analysis, since May 2009. Managed the static timing analysis, timing methodology, circuit simulation and library characterization areas, including EinsTimer, TimeDesign, CRAFT/Alacrite, PowerSpice, ACES, SPECS, iTime, EinsTLT and MAISE tools. In October 2011, took over management of transistor-level timing (EinsTLT) and relinquished the circuit simulation and noise areas to a peer manager.
  • Member, Executive Service Corps. (ESC), a consulting engagement to provide advice to the city of Rio de Janeiro in Brazil towards its preparation for the World Cup Soccer and Summmer Olympics events, September 2010.
  • Manager, circuit and interconnect analysis group, May 2004 to May 2009. Projects in the group include Maise (interconnect reduced order modeling engine including sensitivity analysis), IBMciao (full-wave mixed circuit and electromagnetic solver), Nova (package and chip power delivery and power integrity analysis) and PDAC (Power Delivery Analysis Convergence).
  • EinsStat (IBM internal only): statistical timing analysis and parametric yield prediction of digital integrated circuits.
  • Deft (IBM internal only) derivative-free tuner for small circuit tuning problems.
  • EinsTuner (IBM internal only): gradient-based circuit optimizer based on static timing analysis.
  • JiffyTune (IBM internal only): gradient-based circuit optimizer based on time-domain circuit simulation.
  • SPECS (IBM internal only): fast transistor-level circuit simulator.
  • Backplane-based mixed mode simulation.

Patents

Granted patents

  1. System and method for efficient statistical timing analysis of cycle time independent tests.
    D. J. Hathaway, K. Kalafala, S. Shuma, and C. Visweswariah.
    U. S. Patent 9,280,624, issued March 2016.

  2. Modeling multi-patterning variability with statistical timing.
    B. M. Dreibelbis, J. Dubuque, E. A. Foreman, P. A. Habitz, D. J. Hathaway, J. G. Hemmett, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    U. S. Patent 8,949,765, issued February 2015.

  3. Method of sharing and re-using timing models in a chip across multiple voltage domains.
    E. Fluhr, D. Sinha, S. G. Shuma, N. Venkateswaran, C. Visweswariah, M. H. Wood, and V. Zolotov.
    U. S. patent 8,930,864, issued January 2015.

  4. Systems and methods for correlated parameters in statistical static timing analysis.
    E. A. Foreman, P. A. Habitz, D. J. Hathaway, J. G. Hemmett, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    U. S. patent 8,856,709, issued October 2014.

  5. Reducing runtime and memory requirements of static timing analysis.
    B. M. Dreibelbis, J. Dubuque, E. A. Foreman, D. J. Hathaway, J. G. Hemmett, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    U. S. patent 8,839,167, issued September 2014.

  6. Systems and methods for correlated parameters in statistical static timing analysis.
    E. A. Foreman, P. A. Habitz, D. J. Hathaway, J. G. Hemmett, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    U. S. patent 8,832,652, issued September 2014.

  7. Hierarchical design of integrated circuits with multi-patterning requirements.
    N. C. Buck, B. M. Dreibelbis, J. Dubuque, E. A. Foreman, P. A. Habitz, D. J. Hathaway, J. G. Hemmett, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    U. S. patent 8,850,378, issued September 2014.

  8. Modeling multi-patterning variability with statistical timing.
    B. M. Dreibelbis, J. Dubuque, E. A. Foreman, P. A. Habitz, D. J. Hathaway, J. G. Hemmett, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    U. S. patent 8,806,402, issued August 2014.

  9. Yield computation and optimization for selective voltage binning.
    C. Visweswariah, J. Xiong, and V. Zolotov.
    U. S. patent 8,781,792, issued July 2014.

  10. Decentralized dynamically scheduled parallel static timing analysis.
    D. J. Hathaway, K. Kalafala, M. A. Lavin, J. S. Piaget, and C. Visweswariah.
    U. S. patent 8,775,988, issued July 2014.

  11. System and method for efficient modeling of NPskew effects on static timing tests.
    N. C. Buck, B. M. Dreibelbis, J. Dubuque, E. A. Foreman, P. A. Habitz, J. G. Hemmett, N. Venkateswaran, C. Visweswariah, and X. Wang.
    U. S. patent 8,768,679, issued July 2014.

  12. Parasitic extraction in an integrated circuit with multi-patterning requirements.
    N. C. Buck, B. M. Dreibelbis, J. Dubuque, E. A. Foreman, P. A. Habitz, D. J. Hathaway, J. G. Hemmett, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    U. S. patent 8,769,452, issued July 2014.

  13. Method for achieving an efficient statistical optimization of integrated circuits.
    E. Fluhr, D. Sinha, S. G. Shuma, C. Visweswariah and M. H. Wood.
    U. S. patent 8,732,642, issued May 2014.

  14. Systems and methods for correlated parameters in statistical static timing analysis.
    E. A. Foreman, P. A. Habitz, D. J. Hathaway, J. G. Hemmett, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    U. S. patent 8,707,233, issued April 2014.

  15. System and method for performing static timing analysis in the presence of correlations between asserted arrival times.
    J. Basile, D. J. Hathaway, J. G. Hemmett, K. Kalafala, P. Qi, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    U. S. patent 8,689,158, issued April 2014.

  16. Method and apparatus for selecting voltage and frequency levels for use in at-speed testing.
    J. M. Martinez, C. Visweswariah, F. Woytowich, and J. Xiong.
    U. S. patent 8,676,536, issued March 2014.

  17. Performing statistical timing analysis with non-separable statistical and deterministic variations.
    J. G. Hemmett, D. Sinha, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    U. S. patent 8,683,409, issued March 2014.

  18. Method and device for selectively adding timing margin in an integrated circuit.
    D. Lackey, C. Visweswariah, and P. Zuchowski.
    U. S. patent 8,589,843, issued November 2013.

  19. Device-based random variability modeling in timing analysis.
    M. Bhushan, E. Fluhr, D. Sinha, S. G. Shuma, J. D. Warnock, C. Visweswariah, and M. H. Wood.
    U. S. patent 8,589,842, issued November 2013.

  20. Method of measuring the impact of clock skew on slack during a statistical static timing analysis.
    K. Kalafala, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    U. S. patent 8,578,310, issued November 2013.

  21. Statistical clock cycle computation.
    N. C. Buck, B. M. Dreibelbis, J. Dubuque, E. A. Foreman, J. Gregerson, P. A. Habitz, J. G. Hemmett, D. Sinha, N. Venkateswaran, C. Visweswariah, M. H. Wood, and V. Zolotov.
    U. S. patent 8,560,989, issued October 2013.

  22. Method and device for selectively adding timing margin in an integrated circuit.
    D. Lackey, C. Visweswariah, and P. Zuchowski.
    U. S. patent 8,504,971, issued August 2013.

  23. Ordering of statistical correlated quantities.
    C. Visweswariah, J. Xiong, and V. Zolotov.
    U. S. patent 8,510,696, issued August 2013.

  24. Method and device for selectively adding timing margin in an integrated circuit.
    D. Lackey, C. Visweswariah, and P. Zuchowski.
    U. S. patent 8,490,045, issued July 2013.

  25. Method, system and program storage device for performing a parameterized statistical static timing analysis (SSTA) of an integrated circuit taking into account setup and hold margin interdependence.
    N. C. Buck, B. M. Dreibelbis, J. Dubuque, E. A. Foreman, P. A. Habitz, J. G. Hemmett, N. Venkateswaran, C. Visweswariah, X. Wang, and V. Zolotov.
    U. S. patent 8,468,483, issued June 2013.

  26. Efficient slack projection for truncated distributions.
    E. A. Foreman, J. Gregerson, P. A. Habitz, J. G. Hemmett, D. Sinha, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    U. S. patent 8,458,632, issued June 2013.

  27. Performing statistical timing analysis with non-separable statistical and deterministic variations.
    J. G. Hemmett, D. Sinha, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    U. S. patent 8,418,107, issued April 2013.

  28. Method and apparatus for generating test patterns for use in at-speed testing.
    C. Visweswariah, J. Xiong, and V. Zolotov.
    U. S. patent 8,359,565, issued January 2013.

  29. Moment-based characterization waveform for static timing analysis.
    S. Abbaspour, P. Feldmann, D. D. Ling, and C. Visweswariah.
    U. S. patent 8,359,563, issued January 2013.

  30. Method and apparatus for selecting paths for use in at-speed testing.
    C. Visweswariah, J. Xiong, and V. Zolotov.
    U. S. patent 8,340,939, issued December 2012.

  31. IC chip at-functional-speed testing with process coverage evaluation.
    E. A. Foreman, G. Grise, P. A. Habitz, V. Iyengar, D. Lackey, C. Visweswariah, J. Xiong, and V. Zolotov.
    Korea patent 10-1190433, issued October 2012.

  32. Ordering of statistical correlated quantities.
    C. Visweswariah, J. Xiong, and V. Zolotov.
    U. S. patent 8,266,565, issued September 2012.

  33. IC chip at-functional-speed testing with process coverage evaluation.
    E. A. Foreman, G. Grise, P. A. Habitz, V. Iyengar, D. Lackey, C. Visweswariah, J. Xiong, and V. Zolotov.
    Japan patent 5,090,521, issued September 2012.

  34. System and method of criticality prediction in statistical timing analysis.
    N. Venkateswaran, C. Visweswariah, J. Xiong, and V. Zolotov.
    DE patent 602006031185.0, issued August 2012.

  35. System and method of criticality prediction in statistical timing analysis.
    N. Venkateswaran, C. Visweswariah, J. Xiong, and V. Zolotov.
    GB patent 1,969,502, issued August 2012.

  36. System and method of criticality prediction in statistical timing analysis.
    N. Venkateswaran, C. Visweswariah, J. Xiong, and V. Zolotov.
    EP patent 1,969,502, issued August 2012.

  37. Method and system of evaluating statistical sensitivity credit in path-based hybrid multi-corner static timing analysis.
    N. C. Buck, J. Dubuque, E. A. Foreman, P. A. Habitz, K. Kalafala, P. Qi, C. Visweswariah, and X. Wang.
    Japan patent 5,022,453, issued June 2012.

  38. System and method of criticality prediction in statistical timing analysis.
    N. Venkateswaran, C. Visweswariah, J. Xiong, and V. Zolotov.
    Japan patent 5,004,965, issued June 2012.

  39. Method and apparatus for generating test patterns for use in at-speed testing.
    C. Visweswariah, J. Xiong, and V. Zolotov.
    U. S. patent 8,176,462, issued May 2012.

  40. System and method for efficient analysis of point-to-point delay constraints in static timing.
    R. Banerji, D. J. Hathaway, K. Kalafala, J. M. Sheridan, and C. Visweswariah.
    China patent ZL200710169631.6, issued April 2012.

  41. Methods of performing timing analysis on integrated circuit chips with consideration of process variations.
    E. A. Foreman, P. A. Habitz, D. Sinha, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    U. S. patent 8,141,025, issued March 2012.

  42. Timing closure on multiple selective corners in a single statistical timing run.
    N. C. Buck, B. M. Dreibelbis, J. Dubuque, E. A. Foreman, P. A. Habitz, J. G. Hemmett, S. Lichtensteiger, N. Venkateswaran, C. Visweswariah, and X. Wang.
    U. S. patent 8,141,012, issued March 2012.

  43. A method of performing statistical timing abstraction for hierarchical timing analysis of VLSI circuits.
    A. Bhanji, B. Dorfman, K. Kalafala, D. Sinha, N. Venkateswaran, and C. Visweswariah.
    U. S. patent 8,122,404, issued February 2012.

  44. Method and device for selectively adding timing margin in an integrated circuit.
    D. Lackey, C. Visweswariah, and P. Zuchowski.
    U. S. patent 8,122,409, issued February 2012.

  45. Affinity-based clustering of vectors for partitioning the columns of a matrix.
    K. Kalafala, V. B. Rao, and C. Visweswariah.
    U. S. patent 8,112,735, issued February 2012.

  46. Method and apparatus for efficient incremental statistical timing analysis and optimization.
    D. Sinha, N. Venkateswaran, C. Visweswariah, J. Xiong, and V. Zolotov.
    U. S. patent 8,104,005, issued January 2012.

  47. Method and system of evaluating statistical sensitivity credit in path-based hybrid multi-corner static timing analysis.
    N. C. Buck, J. Dubuque, E. A. Foreman, P. A. Habitz, K. Kalafala, P. Qi, C. Visweswariah, and X. Wang.
    Korea patent 1,091,396, issued December 2011.

  48. Methods for statistical slew propagation during block-based statistical static timing analysis.
    J. G. Hemmett, C. Visweswariah, and V. Zolotov.
    U. S. patent 8,086,976, issued December 2011.

  49. Chip design and fabrication method optimized for profit.
    N. C. Buck, H. Chen, J. Eckhardt, E. A. Foreman, J. Gregerson, P. A. Habitz, S. Lichtensteiger, C. Visweswariah, and T. Wilder.
    U. S. patent 8,086,988, issued December 2011.

  50. Method and system for analyzing cross-talk coupling noise events in block-based statistical static timing.
    N. C. Buck, B. M. Dreibelbis, J. Dubuque, E. A. Foreman, P. A. Habitz, D. J. Hathaway, G. M. Schaeffer, and C. Visweswariah.
    U. S. patent 8,056,035, issued November 2011.

  51. System and method for accommodating non-Gaussian and nonlinear sources of variation in statistical static timing analysis.
    H. Chang, S. Narayan, C. Visweswariah, and V. Zolotov.
    U. S. patent 8,015,525, issued September 2011.

  52. System and method for statistical timing analysis of digital circuits.
    C. Visweswariah.
    U. S. patent 8,010,921, issued August 2011.

  53. Method and apparatus for covering a multilayer process space during at-speed testing.
    Y. Shi, C. Visweswariah, J. Xiong, and V. Zolotov.
    U. S. patent 7,971,120, issued June 2011.

  54. Affinity-based clustering of vectors for partitioning the columns of a matrix.
    K. Kalafala, V. B. Rao, and C. Visweswariah.
    U. S. patent 7,958,484, issued June 2011.

  55. Method for identifying failing timing requirement in a digital design.
    N. C. Buck, J. Dubuque, E. A. Foreman, P. A. Habitz, and C. Visweswariah.
    U. S. patent 7,886,246, issued February 2011.

  56. Method and apparatus for statistical path selection for at-speed testing.
    H. Fatemi, C. Visweswariah, J. Xiong, and V. Zolotov.
    U. S. patent 7,886,247, issued February 2011.

  57. Method and apparatus for computing test margins for at-speed testing.
    C. Visweswariah, J. Xiong, and V. Zolotov.
    U. S. patent 7,873,925, issued January 2011.

  58. Method and apparatus for incrementally computing criticality and yield gradient.
    C. Visweswariah, J. Xiong, and V. Zolotov.
    U. S. patent 7,861,199, issued December 2010.

  59. System and method for generating at-speed structural tests to improve process and environmental parameter space coverage.
    G. Grise, P. A. Habitz, V. Iyengar, D. Lackey, C. Visweswariah, and V. Zolotov.
    U. S. patent 7,856,607, issued December 2010.

  60. Methods for conserving memory in statistical static timing analysis.
    J. G. Hemmett, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    U. S. patent 7,849,429, issued December 2010.

  61. Method to identify timing violations outside of manufacturing specification limits.
    N. C. Buck, J. Dubuque, E. A. Foreman, P. A. Habitz, and C. Visweswariah.
    U. S. patent 7,844,932, issued November 2010.

  62. System and method of criticality prediction in statistical timing analysis.
    N. Venkateswaran, C. Visweswariah, J. Xiong, and V. Zolotov.
    Korea patent 998,798, issued November 2010.

  63. Representing and propagating a variational voltage waveform in statistical static timing analysis of digital circuits.
    S. Abbaspour, D. J. Hathaway, C. Visweswariah, J. Xiong, and V. Zolotov.
    U. S. patent 7,814,448, issued October 2010.

  64. Method and apparatus for static timing analysis in the presence of a coupling event and process variation.
    S. Abbaspour, G. M. Schaeffer, and C. Visweswariah.
    China patent ZL200810002926.9, issued September 2010.

  65. Parameter ordering for multi-corner static timing analysis.
    N. C. Buck, J. Dubuque, E. A. Foreman, P. A. Habitz, K. Kalafala, P. Qi, C. Visweswariah, and X. Wang.
    U. S. patent 7,797,657, issued September 2010.

  66. System and method of criticality prediction in statistical timing analysis.
    N. Venkateswaran, C. Visweswariah, J. Xiong, and V. Zolotov.
    China patent ZL200680044096.5, issued July 2010.

  67. Method of achieving timing closure in digital integrated circuits by optimizing individual macros.
    D. J. Hathaway, C. Visweswariah, P. M. Williams, and J. Zhou.
    U. S. patent 7,743,355, issued June 2010.

  68. Method and apparatus for static timing analysis in the presence of a coupling event and process variation.
    S. Abbaspour, G. M. Schaeffer, and C. Visweswariah.
    U. S. patent 7,739,640, issued June 2010.

  69. System and method for efficient analysis of point-to-point delay constraints in static timing.
    R. Banerji, D. J. Hathaway, K. Kalafala, J. M. Sheridan, and C. Visweswariah.
    U. S. patent 7,698,674, issued April 2010.

  70. Variable threshold system and method for multi-corner static timing analysis.
    N. C. Buck, J. Dubuque, E. A. Foreman, P. A. Habitz, K. Kalafala, P. Qi, C. Visweswariah, and X. Wang.
    U. S. patent 7,681,157, issued March 2010.

  71. IC chip at-functional-speed testing with process coverage evaluation.
    E. A. Foreman, G. Grise, P. A. Habitz, V. Iyengar, D. Lackey, C. Visweswariah, J. Xiong, and V. Zolotov.
    U. S. patent 7,620,921, issued November 2009.

  72. System and method for statistical timing analysis of digital circuits.
    C. Visweswariah.
    Taiwan patent I311,717, issued July 2009.

  73. Method and system of evaluating statistical sensitivity credit in path-based hybrid multi-corner static timing analysis.
    N. C. Buck, J. Dubuque, E. A. Foreman, P. A. Habitz, K. Kalafala, P. Qi, C. Visweswariah, and X. Wang.
    U. S. patent 7,555,740, issued June 2009.

  74. Method, system and program product for accommodating a spatially correlated source of variation in statistical timing analysis.
    N. Venkateswaran, C. Visweswariah, L. Zhang, and V. Zolotov.
    China patent ZL200610143551.9, issued June 2009.

  75. System and method for incremental statistical timing analysis of digital circuits.
    C. Visweswariah.
    U. S. patent 7,512,919, issued March 2009.

  76. Method, system, and program product for computing a yield gradient from statistical timing.
    C. Visweswariah, J. Xiong, and V. Zolotov.
    U. S. patent 7,480,880, issued January 2009.

  77. System and method of criticality prediction in statistical timing analysis.
    N. Venkateswaran, C. Visweswariah, J. Xiong, and V. Zolotov.
    U. S. patent 7,437,697, issued October 2008.

  78. System and method for statistical timing analysis of digital circuits.
    C. Visweswariah.
    U. S. patent 7,428,716, issued September 2008.

  79. Affinity-based clustering of vectors for partitioning the columns of a matrix.
    K. Kalafala, V. B. Rao, and C. Visweswariah.
    U. S. patent 7,353,359, issued April 2008.

  80. System and method for statistical timing analysis of digital circuits.
    C. Visweswariah.
    Japan patent 4,061,295, issued December 2007.

  81. System and method for statistical timing analysis of digital circuits.
    C. Visweswariah.
    China patent ZL200410078630.7, issued November 2007.

  82. System and method for accommodating non-Gaussian and nonlinear sources of variation in statistical static timing analysis.
    H. Chang, S. Narayan, C. Visweswariah, and V. Zolotov.
    U. S. patent 7,293,248, issued November 2007.

  83. Method, system and program product for accommodating a spatially correlated source of variation in statistical timing analysis.
    N. Venkateswaran, C. Visweswariah, L. Zhang, and V. Zolotov.
    U. S. patent 7,212,946, issued May 2007.

  84. System and method for correlated process pessimism removal for static timing analysis.
    K. Kalafala, P. Qi, A. J. Suess, D. J. Hathaway, and C. Visweswariah.
    U. S. patent 7,117,466, issued October 2006.

  85. System and method for derivative-free optimization of electrical circuits.
    S. G. Walker, C. Visweswariah, K. Scheinberg, and P. J. Restle.
    U. S. patent 7,117,455, issued October 2006.

  86. System and method for incremental statistical timing analysis of digital circuits.
    C. Visweswariah.
    U. S. patent 7,111,260, issued September 2006.

  87. Method for tuning a digital design for synthesized random logic circuit macros in a continuous design space with optional insertion of multiple threshold voltage devices.
    E. K. Cho, D. J. Hathaway, M-T. Hsu, L. K. Lange, G. A. Northrop, C. Visweswariah, C. Washburn, P. M. Williams, and J. Zhou.
    U. S. patent 7,093,208, issued August 2006.

  88. System and method for probabilistic criticality prediction of digital circuits.
    C. Visweswariah.
    U. S. patent 7,086,023, issued August 2006.

  89. Method of optimizing and analyzing selected portions of a digital integrated circuit.
    D. J. Hathaway, L. K. Lange, C. Visweswariah, and P. M. Williams.
    U. S. patent 7,010,763, issued March 2006.

  90. Method of achieving timing closure in digital integrated circuits by optimizing individual macros.
    D. J. Hathaway, C. Visweswariah, P. M. Williams, and J. Zhou.
    U. S. patent 7,003,747, issued February 2006.

  91. System and method for optimal waveform shaping.
    C. Visweswariah.
    U. S. patent 6,922,819, issued July 2005.

  92. Parameter variation tolerant method for circuit design optimization.
    X. Bai, D. J. Hathaway, P. N. Strenski, and C. Visweswariah.
    U. S. patent 6,826,733, issued November 2004.

  93. Method of reformulating static circuit optimization problems for reduced size, degeneracy and redundancy.
    A. R. Conn and C. Visweswariah.
    U. S. patent 6,321,362, issued November 2001.

  94. Method for incorporating noise considerations in automatic circuit optimization.
    A. R. Conn, R. A. Haring, and C. Visweswariah.
    U. S. patent 5,999,714, issued December 1999.

  95. Method of efficient gradient computation.
    A. R. Conn, R. A. Haring, and C. Visweswariah.
    U. S. patent 5,886,908, issued March 1999.

Patents in the pipeline

  1. Method for accurately timing boundary gates with hierarchical timing abstracts.
    H. Gupta, D. Sinha, and C. Visweswariah.
    Docket FIS-9-2015-0195-US1, to be filed.

  2. System and method of sensitivity calculation filtering for statistical static timing analysis.
    N. Buck, E. A. Foreman, J. G. Hemmett, K. Kalafala, G. M. Schaeffer, S. Shuma, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    Docket BUR-9-2015-0106-US1, to be filed.

  3. Method for optimizing chip operation with dynamic frequency scaling.
    N. Buck, E. A. Foreman, J. G. Hemmett, K. Kalafala, G. M. Schaeffer, S. Shuma, N. Venkateswaran, C. Visweswariah, M. H. Wood, and V. Zolotov.
    Docket BUR-9-2015-0104-US1, to be filed.

  4. System and method for optimal corner selection using statistical timing.
    E. A. Foreman, J. G. Hemmett, K. Kalafala, G. M. Schaeffer, S. Shuma, A. Suess, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    Docket BUR-9-2015-0100-US1, to be filed.

  5. Prioritized path tracing in statistical timing analysis of integrated circuits.
    V. Rao, D. Sinha, and C. Visweswariah.
    Docket FIS-9-2015-0118-US1, filed August 2015.

  6. Automated timing analysis.
    K. Kalafala, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    Docket FIS-9-2015-0106-US1, filed September 2015.

  7. A method and apparatus for identifying changes in health and status of assets from continuous image feeds in near real time.
    Y. Kim, A. Raman, and C. Visweswariah.
    Docket YOR-8-2014-1045, to be evaluted.

  8. Method of hierarchical timing closure employing dynamic load sensitive feedback constraints,
    A. Bhanji, K. Kalafala, R. Ledalla, D. Sinha, C. Visweswariah, and M. H. Wood.
    Docket FIS-9-2015-0035-US1, filed April 2015.

  9. Dynamic and adaptive timing sensitivity during static timing analysis using look-up table.
    N. Buck, B. M. Dreibelbis, J. Dubuque, E. A. Foreman, J. G. Hemmett, K. Kalafala, G. M. Schaeffer, S. Shuma, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    Docket BUR-9-2015-0062-US1, filed June 2015.

  10. Variable accuracy parameter modeling in statistical timing.
    E. A. Foreman, J. G. Hemmett, K. Kalafala, G. M. Schaeffer, S. Shuma, A. Suess, C. Visweswariah, and M. H. Wood.
    Docket BUR-9-2015-0058-US1, filed June 2015.

  11. Collapsing terms in statistical static timing analysis.
    E. A. Foreman, J. G. Hemmett, C. Visweswariah, and V. Zolotov.
    Docket BUR-9-2014-0110-US1, filed March 2015.

  12. Partial parameters and projection thereof included within statistical timing analysis.
    B. M. Dreibelbis, J. Dubuque, E. A. Foreman, J. G. Hemmett, L. Pickup, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    Docket BUR-9-2013-0040-US1, filed February 2014.

  13. Modeling multi-patterning variability with statistical timing.
    N. Buck, B. M. Dreibelbis, J. Dubuque, E. A. Foreman, P. A. Habitz, D. J. Hathaway, J. G. Hemmett, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    Docket BUR-9-2012-0043-US3, filed November 2014.

  14. Modeling multi-patterning variability with statistical timing.
    N. Buck, B. M. Dreibelbis, J. Dubuque, E. A. Foreman, P. A. Habitz, D. J. Hathaway, J. G. Hemmett, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    Docket BUR-9-2012-0043-CN1, filed October 2013.

  15. Hierarchical design of integrated circuits with multi-patterning requirements.
    N. C. Buck, B. M. Dreibelbis, J. Dubuque, E. A. Foreman, P. A. Habitz, D. J. Hathaway, J. G. Hemmett, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    Docket BUR-9-2012-0102-US2, filed August 2014.

  16. Hierarchical design of integrated circuits with multi-patterning requirements.
    N. C. Buck, B. M. Dreibelbis, J. Dubuque, E. A. Foreman, P. A. Habitz, D. J. Hathaway, J. G. Hemmett, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    Docket BUR-9-2012-0102-CN1, filed October 2013.

  17. Parasitic extraction in an integrated circuit with multi-patterning requirements.
    N. C. Buck, B. M. Dreibelbis, J. Dubuque, E. A. Foreman, P. A. Habitz, D. J. Hathaway, J. G. Hemmett, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    Docket BUR-9-2012-0103-US2, filed December 2013.

  18. Parasitic extraction in an integrated circuit with multi-patterning requirements.
    N. C. Buck, B. M. Dreibelbis, J. Dubuque, E. A. Foreman, P. A. Habitz, D. J. Hathaway, J. G. Hemmett, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    Docket BUR-9-2012-0103-CN1, filed October 2013.

  19. Integrating manufacturing feedback into integrated circuit strucutre design.
    N. C. Buck, B. M. Dreibelbis, J. Dubuque, E. A. Foreman, P. A. Habitz, J. G. Hemmett, N. Venkateswaran, C. Visweswariah, X. Wang, and V. Zolotov.
    Docket BUR-9-2011-0019-US1, filed July 2011.

  20. Timing closure on multiple selective corners in a single statistical timing run.
    N. C. Buck, B. M. Dreibelbis, J. Dubuque, E. A. Foreman, P. A. Habitz, J. G. Hemmett, S. Lichtensteiger, N. Venkateswaran, C. Visweswariah, and X. Wang.
    Docket BUR-9-2009-0032-IN1, filed June 2010 in India.

  21. Method and apparatus for efficient incremental statistical timing analysis and optimization.
    D. Sinha, N. Venkateswaran, C. Visweswariah, J. Xiong, and V. Zolotov.
    Docket YOR-9-2008-0317-IN1, filed September 2009 in India.

  22. Method and system of evaluating statistical sensitivity credit in path-based hybrid multi-corner static timing analysis.
    N. Buck, J. Dubuque, E. A. Foreman, P. A. Habitz, K. Kalafala, P. Qi, C. Visweswariah, and X. Wang.
    Docket BUR-9-2006-0236-PCT1 filed February 2008 in PCT.

  23. IC chip at-functional-speed testing with process coverage evaluation.
    E. A. Foreman, G. Grise, P. A. Habitz, V. Iyengar, D. Lackey, C. Visweswariah, J. Xiong, and V. Zolotov.
    Docket BUR-9-2006-0235-PCT1 filed April 2008 in PCT.
    Docket BUR-9-2006-0235-TW1 filed April 2008 in Taiwan.

  24. System and method of criticality prediction in statistical timing analysis.
    N. Venkateswaran, C. Visweswariah, J. Xiong, and V. Zolotov.
    Docket YOR-9-2005-0245-PCT1 filed December 2006 in PCT.

Publications

Book

  1. Electronic circuit and system simulation methods.
    L. T. Pillage, R. A. Rohrer, and C. Visweswariah.
    McGraw-Hill, 1995.

Book chapter

  1. Electrical and timing simulation.
    C. Visweswariah.
    In Encyclopedia of Electrical and Electronics Engineering, J. G. Webster, Editor, volume 6, pages 229--238, John Wiley and Sons, 1999.

Invited publications

  1. Future energy systems: the role of analytics and optimization.
    C. Visweswariah,
    Keynote speech, EPRI Innovation Summit, Dublin, Ireland, June 2014.

  2. Statistical timing analysis for high-performance processors.
    C. Visweswariah.
    Invited lecture hosted by the IEEE Solid State Society, Indian Institute of Science, Bengaluru, India, October 2012.

  3. Statistical timing analysis for high-performance processors.
    C. Visweswariah.
    Invited lecture, Indian Institute of Technology, Chennai, India, October 2012.

  4. The future of timing: {divide and conquer}4.
    C. Visweswariah.
    ACM/IEEE workshop on timing issues in the specification and synthesis of digital systems (TAU), Taipei, Taiwan, January 2012.

  5. Robust optimization of digital circuits: progress and challenges.
    C. Visweswariah.
    Invited lecture, Electrical and Computer Engineering Department, University of Wisconsin, Madison, WI, February 2011.

  6. Challenges in robust optimization of digital integrated circuits.
    C. Visweswariah.
    Invited lecture, Institute for Pure and Applied Mathematics (IPAM) Workshop on Robust Optimization, University of California, Los Angeles, CA, November 2010.

  7. How I built a zero carbon footprint house.
    C. Visweswariah.
    Invited lecture, International Workshop on Emerging Circuits and Systems (IWECS), Hefei, China, August 2010.

  8. How I built a carbon-neutral house.
    C. Visweswariah.
    Invited lecture, Electrical Engineering and Computer Science department, University of California, Berkeley, CA, March 2010.

  9. Statistical timing: where's the tofu?
    N. C. Buck, E. A. Foreman, P. A. Habitz, J. G. Hemmett, S. G. Shuma, N. Venkateswaran, C. Visweswariah, and X. Wang.
    Invited special session at International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2009.

  10. Efficient modeling of spatial correlations for parameterized statistical static timing analysis.
    J. Xiong, V. Zolotov, and C. Visweswariah.
    ASICON, Changsha, China, October 2009.

  11. At-speed testing in the face of process variations.
    Abstract.
    C. Visweswariah, V. Zolotov and J. Xiong.
    VLSI Test Symposium (VTS), Santa Cruz, CA, May 2009.

  12. Statistical power analysis for high-performance processors.
    H. Chen, S. Neely, J. Xiong, V. Zolotov, and C. Visweswariah.
    Journal of Low Power Electronics (JOLPE), volume 5, number 1, April 2009, pages 70--76.

  13. Statistical timing: where's the tofu?
    N. C. Buck, E. A. Foreman, P. A. Habitz, J. G. Hemmett, S. G. Shuma, N. Venkateswaran, C. Visweswariah, and X. Wang.
    ACM/IEEE workshop on timing issues in the specification and synthesis of digital systems (TAU), Austin, TX, February 2009.

  14. Robustness and quality in the face of variability.
    C. Visweswariah.
    Keynote speech, International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 2008.

  15. Within-die variations in timing: from derating to CPPR to statistical methods.
    C. Visweswariah.
    Full-day tutorial, International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2007.

  16. Statistical techniques to combat variability and achieve robust design.
    C. Visweswariah.
    Invited talk at Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), Sapporo, Japan, October 2007.

  17. The end of traditional CMOS.
    C. Visweswariah.
    Panel opening statement at Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), Sapporo, Japan, October 2007.

  18. Statistical techniques for robust digital design.
    C. Visweswariah.
    Invited seminar, University of Texas, Austin, TX, March 2007.

  19. Fear, uncertainty and statistics.
    C. Visweswariah.
    Invited talk, International Symposium on Physical Design (ISPD), March 2007, Austin, TX.
    Click here for charts.

  20. What engineers want.
    C. Visweswariah.
    Panel opening statement, Banff International Research Station for Mathematical Innovation and Discovery (BIRS) workshop on "Optimization and Engineering," November 2006, Banff, Alberta, Canada.

  21. Challenges in statistical timing and optimization of integrated circuits.
    C. Visweswariah.
    Invited presentation at Banff International Research Station for Mathematical Innovation and Discovery (BIRS) workshop on "Optimization and Engineering," November 2006, Banff, Alberta, Canada.

  22. Statistical timing in a practical 65 nm robust design flow.
    C. Visweswariah.
    Invited presentation at the C2S2 workshop on Robust Circuit Design, Berkeley, CA, July 2006.

  23. Statistical analysis and optimization in the presence of gate and interconnect delay variations.
    C. Visweswariah.
    Invited presentation at System Level Interconnect Prediction (SLIP), Munich, Germany, page 37, March 2006. Click here for charts.

  24. Can innovation be nurtured?
    C. Visweswariah.
    Invited article for a special issue of EE Times focusing on innovation, December 2005.

  25. Statistical analysis and design of digital integrated circuits.
    C. Visweswariah.
    Invited presentation at EDA Forum '05, Hanover, Germany, November 2005.

  26. Mathematics and engineering: a clash of cultures?
    C. Visweswariah.
    Invited presentation at the Industrial Optimization Seminar Series, The Fields Institute for Research in Mathematical Sciences, Toronto, Canada, May 2005. Click here for streaming audio.

  27. Spread sheet studies on the impact of variability.
    C. Visweswariah.
    Invited presentation at the International Conference on Integrated Circuit Design and Technology (ICICDT '05), Austin, TX, May 2005.

  28. Statistical analysis and design: from picoseconds to probabilities.
    C. Visweswariah.
    Invited tutorial at 17th Symposium on Integrated Circuits and Systems Design (SBCCI), Porto de Galinhas, Brazil, September 2004.

  29. Invited panel statement: New challenges in IC design.
    C. Visweswariah.
    17th Symposium on Integrated Circuits and Systems Design (SBCCI), Porto de Galinhas, Brazil, September 2004.

  30. Invited panel statement: Is statistical timing statistically significant?
    C. Visweswariah.
    Design Automation Conference (DAC), San Diego, CA, June 2004.

  31. Statistical timing of digital integrated circuits.
    C. Visweswariah.
    IEEE International Solid-State Circuits Conference (ISSCC), Advanced Digital Solid-State Circuits Forum, San Francisco, CA, February 2004.

  32. Death, taxes and failing chips.
    C. Visweswariah.
    Design Automation Conference (DAC), Anaheim, CA, pages 343--347, June 2003.

  33. Death, taxes and failing chips.
    C. Visweswariah.
    ACM/IEEE workshop on timing issues in the specification and synthesis of digital systems (TAU), Monterey, CA, December 2002.

  34. Optimization challenges in transistor sizing.
    C. Visweswariah.
    Workshop on Multilevel Optimization in VLSICAD, Institute for Pure and Applied Mathematics (IPAM), University of California at Los Angeles, December 2001.

  35. Overview of continuous optimization advances and applications to circuit tuning.
    A. R. Conn and C. Visweswariah.
    International Symposium on Physical Design (ISPD), April 2001, Sonoma County, CA.

  36. Formal static optimization of high-performance digital circuits.
    C. Visweswariah.
    ACM/IEEE workshop on timing issues in the specification and synthesis of digital systems (TAU), page 51, December 2000, Austin TX.

  37. Algorithms for formal circuit optimization on a static timing basis. (Part of the full-day tutorial "Static timing analysis and optimization for high-performance digital design success.")
    C. Visweswariah.
    Design Automation Conference (DAC), Los Angeles, CA, June 2000.

  38. Optimization techniques for high-performance digital circuits.
    C. Visweswariah.
    IEEE International Conference on Computer-Aided Design embedded tutorial, San Jose, CA, pages 198--205, November 1997.
    Presentation slides can be viewed by clicking here.

  39. Circuit tuning for high-performance custom digital design.
    C. Visweswariah, S. Sapatnekar, and S. R. Nassif.
    IEEE International Conference on Computer-Aided Design Tutorial, San Jose, CA, November 1996.

  40. Efficient time-domain simulation and optimization of digital FET circuits.
    A. R. Conn, R. A. Haring, and C. Visweswariah.
    Mathematical Theory of Networks and Systems, St. Louis, MO, May 1996.

Refereed publications

  1. Transistor sizing of custom high-performance digital circuits with parametric yield considerations.
    D. K. Beece, C. Visweswariah, J. Xiong, and V. Zolotov.
    Journal of Optimization and Engineering, Volume 15, Issue 1, 2014, pages 217--241.

  2. Order statistics for correlated random variables and its application to at-speed testing.
    Y. Shi, J. Xiong, V. Zolotov and C. Visweswariah.
    ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 18, No. 3, Article 42, July 2013.

  3. Speeding up computation of the max/min of a set of Gaussians for statistical timing analysis and optimization.
    V. A. Kuruvilla, D. Sinha, J. S. Piaget, C. Visweswariah, and N. Chandrachoodan.
    Design Automation Conference (DAC), Austin, TX, June 2013.

  4. Converged statistical timing flow supporting different business models.
    S. G. Shuma, E. A. Foreman, N. C. Buck, C. Visweswariah, M. H. Wood, and R. J. Allen.
    Design Automation Conference (DAC) user track, Austin, TX, June 2013.

  5. Multi-threaded statistical static timing analysis on multi-million instance 32nm designs.
    K. Kalafala, E. A. Foreman, C. Visweswariah, D. N. Netrabile, J. S. Piaget, M. A. Lavin, J. G. Hemmett, V. Zolotov, G. M. Schaeffer, J. W. Staten, and S. D. Meyers.
    Design Automation Conference (DAC) user track, Austin, TX, June 2013.

  6. Speeding up computation of the max/min of a set of Gaussians for statistical timing analysis and optimization.
    V. A. Kuruvilla, D. Sinha, J. S. Piaget, C. Visweswariah, and N. Chandrachoodan.
    ACM/IEEE workshop on timing issues in the specification and synthesis of digital systems (TAU), Lake Tahoe, NV, March 2013.

  7. A dynamic method for efficient random mismatch characterization of standard cells.
    W. Zhang, A. Singhee, J. Xiong, P. Habitz, A. Joshi, C. Visweswariah, and J. Sundquist.
    International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2012.

  8. A dynamic method for efficient random mismatch characterization of standard cells.
    W. Zhang, A. Singhee, J. Xiong, P. Habitz, A. Joshi, C. Visweswariah, and J. Sundquist.
    IEEE Design for Manufacturability and Yield (DFMY) workshop, San Francisco, CA, June 2012.

  9. Reversible statistical max/min operation: theory and applications to timing.
    D. Sinha, C. Visweswariah, J. Xiong, V. Zolotov, and N. Venkateswaran.
    Design Automation Conference (DAC), San Francisco, CA, June 2012.

  10. Timing analysis with nonseparable statistical and deterministic variations.
    V. Zolotov, D. Sinha, J. Hemmett, E. A. Foreman, C. Visweswariah, J. Xiong, and J. Leitzen.
    Design Automation Conference (DAC), San Francisco, CA, June 2012.

  11. A practical statistical performance path test methodology and its application.
    J. Xiong, J. Bickford, K. Bercaw, V. Iyengar, P. Gillis, J. Martinez, F. Woytowich, C. Visweswariah, and V. Zolotov.
    Design Automation Conference (DAC) user track, San Francisco, CA, June 2012.

  12. Coupling-aware statistical timing analysis.
    H. Chan, N. C. Buck, B. Dreibelbis, E. A. Foreman, J. Dubuque, P. Habitz, D. Hathaway, G. M. Schaeffer, and C. Visweswariah.
    Design Automation Conference (DAC) user track, San Francisco, CA, June 2012.

  13. A novel method for reducing metal variation with statistical static timing analysis.
    E. A. Foreman, P. A. Habitz, M-C. Cheng, and C. Visweswariah.
    IEEE Transactions on Computer-Aided Design of ICs and Systems, volume 31, number 8, August 2012.

  14. A dynamic method for efficient random mismatch characterization of standard cells.
    W. Zhang, A. Singhee, J. Xiong, P. Habitz, A. Joshi, C. Visweswariah, and J. Sundquist.
    ACM/IEEE workshop on timing issues in the specification and synthesis of digital systems (TAU), Taipei, Taiwan, January 2012, pages 37--42.

  15. Reversible statistical max/min operation: theory and applications to timing.
    D. Sinha, C. Visweswariah, J. Xiong, V. Zolotov, and N. Venkateswaran.
    ACM/IEEE workshop on timing issues in the specification and synthesis of digital systems (TAU), Taipei, Taiwan, January 2012, pages 16--21.

  16. Timing analysis with nonseparable statistical and deterministic variations.
    V. Zolotov, D. Sinha, J. Hemmett, E. A. Foreman, C. Visweswariah, J. Xiong, and J. Leitzen.
    ACM/IEEE workshop on timing issues in the specification and synthesis of digital systems (TAU), Taipei, Taiwan, January 2012, pages 4--9.

  17. Highly scalable multi-threaded incremental static timing analysis.
    D. Beece, B. Chen, H. Gupta, D. Hathaway, K. Kalafala. D. Keller, M. A. Lavin, J. S. Piaget, P. Qi, G. M. Schaeffer, C. Visweswariah, J. Wilson, and V. Zolotov.
    Workshop on Parallel Algorithms, Programming and Architectures (PAPA) poster, San Diego, CA, June 2011.

  18. Transistor sizing of custom high-performance digital circuits with parametric yield considerations.
    D. K. Beece, J. Xiong, C. Visweswariah, V. Zolotov, and Y. Liu.
    Design Automation Conference (DAC), Anaheim, CA, June 2010.

  19. Statistical path selection for at-speed test.
    V. Zolotov, J. Xiong, H. Fatemi, and C. Visweswariah.
    IEEE Transactions on Computer-Aided Design of ICs and Systems, volume 29, number 5, May 2010, pages 749--759.

  20. Voltage binning under process variation.
    V. Zolotov, C. Visweswariah, and J. Xiong.
    International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2009.

  21. Pre-ATPG path selection for near optimal post-ATPG process space coverage.
    J. Xiong, Y. Shi, V. Zolotov, and C. Visweswariah.
    International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2009.

  22. Optimal test margin computation for at-speed structural test.
    J. Xiong, V. Zolotov, C. Visweswariah, and P. A. Habitz.
    IEEE Transactions on Computer-Aided Design of ICs and Systems, volume 28, number 9, September 2009, pages 1414--1423.

  23. A new methodology for power-aware transistor sizing: Free Power Recovery (FPR).
    M. Vratonjic, M. Ziegler, G. Gristede, V. Zyuban, T. Mitchell, E. Cho, C. Visweswariah, and V. Oklobdzija.
    Power and Timing Modeling, Optimization and Simulation (PATMOS), Delft, The Netherlands, September 2009.

  24. A hierarchical transistor and gate level statistical timing analysis flow for microprocessor designs.
    D. Sinha, A. Bhanji, C. Visweswariah, G. Ditlow, K. Kalafala, N. Venkateswaran, and S. Gupta.
    Design Automation Conference user track, San Francisco, CA, July 2009.

  25. A moment-based effective characterization waveform for static timing analysis.
    D. D. Ling, S. Abbaspour, C. Visweswariah and P. Feldmann.
    Design Automation Conference, San Francisco, CA, July 2009, pages 19--24.

  26. Statistical multilayer process space coverage for at-speed test.
    J. Xiong, Y. Shi, V. Zolotov, and C. Visweswariah.
    Design Automation Conference, San Francisco, CA, July 2009.

  27. Statistical ordering of correlated timing quantities and its application for path ranking.
    J. Xiong, C. Visweswariah, and V. Zolotov.
    Design Automation Conference, San Francisco, CA, July 2009.

  28. Aggressor set selection under constraints for maximum crosstalk noise.
    D. Sinha, A. Rubin, C. Visweswariah, F. Borkam, G. M. Schaeffer, and S. Abbaspour.
    IEEE Transactions on Computer-Aided Design of ICs and Systems, volume 28, number 7, pages 1096--1100, July 2009.

  29. Statistical multilayer process space coverage for at-speed test.
    J. Xiong, Y. Shi, V. Zolotov, and C. Visweswariah.
    IEEE North Atlantic Test Workshop (NATW), Hopewell Junction, NY, May 2009.

  30. Statistical ordering of correlated timing quantities and its application for path ranking.
    J. Xiong, C. Visweswariah, and V. Zolotov.
    IEEE North Atlantic Test Workshop (NATW), Hopewell Junction, NY, May 2009.

  31. Test generation for process variation delay defects.
    V. Zolotov, C. Visweswariah, and J. Xiong.
    IEEE North Atlantic Test Workshop (NATW), Hopewell Junction, NY, May 2009.

  32. A hierarchical transistor and gate level statistical timing analysis flow for microprocessor designs.
    D. Sinha, A. Bhanji, C. Visweswariah, G. Ditlow, K. Kalafala, N. Venkateswaran, and S. Gupta.
    ACM/IEEE workshop on timing issues in the specification and synthesis of digital systems (TAU), Austin, TX, February 2009, pages 1--4.

  33. A moment-based effective characterization waveform for static timing analysis.
    D. D. Ling, S. Abbaspour, C. Visweswariah and P. Feldmann.
    ACM/IEEE workshop on timing issues in the specification and synthesis of digital systems (TAU), Austin, TX, February 2009, pages 85--90.

  34. Statistical multilayer process space coverage for at-speed test.
    J. Xiong, Y. Shi, V. Zolotov, and C. Visweswariah.
    ACM/IEEE workshop on timing issues in the specification and synthesis of digital systems (TAU), Austin, TX, February 2009, pages 55--60.

  35. Statistical ordering of correlated timing quantities and its application for path ranking.
    J. Xiong, C. Visweswariah, and V. Zolotov.
    ACM/IEEE workshop on timing issues in the specification and synthesis of digital systems (TAU), Austin, TX, February 2009, pages 43--48.

  36. Statistical path selection for at-speed test.
    V. Zolotov, J. Xiong, H. Fatemi, and C. Visweswariah.
    International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2008.

  37. Statistical modeling and analysis of static leakage and dynamic switching power.
    H. Chen, S. Neely, J. Xiong, V. Zolotov, and C. Visweswariah.
    Power and Timing Modeling, Optimization and Simulation (PATMOS), Lisbon, Portugal, September 2008.

  38. Statistical test to uncover process variations.
    V. Iyengar, J. Xiong, S. Venkatesan, V. Zolotov, D. Lackey, P. Habitz, and C. Visweswariah.
    IEEE North Atlantic Test Workshop (NATW), Boxborough, MA, pages 158--164, May 2008.

  39. Optimal margin computation for at-speed test.
    J. Xiong, V. Zolotov, C. Visweswariah, and P. A. Habitz.
    Design Automation and Test in Europe (DATE), Messe Munich, Germany, pages 602--607, March 2008.

  40. Incremental criticality and yield gradients.
    J. Xiong, V. Zolotov and C. Visweswariah.
    Design Automation and Test in Europe (DATE), Messe Munich, Germany, pages 1130--1135, March 2008.

  41. Static timing: back to our roots.
    R. Chen, L. Zhang, V. Zolotov, C. Visweswariah, and J. Xiong.
    Asia and South Pacific Design Automation Conference (ASPDAC), Seoul, Korea, pages 310--315, January 2008.

  42. Compact modeling of variational waveforms.
    V. Zolotov, J. Xiong, S. Abbaspour, D. J. Hathaway, and C. Visweswariah.
    International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2007.

  43. Variation-aware performance verification using at-speed structural test and statistical timing.
    V. Iyengar, J. Xiong, S. Venkatesan, V. Zolotov, D. Lackey, P. Habitz, and C. Visweswariah.
    International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2007.

  44. Static timing: back to our roots.
    R. Chen, E. A. Foreman, P. A. Habitz, J. G. Hemmett, K. Kalafala, J. S. Piaget, P. Qi, N. Venkateswaran, C. Visweswariah, J. Xiong, and V. Zolotov.
    ACM/IEEE workshop on timing issues in the specification and synthesis of digital systems (TAU), Austin, TX, pages 130--136, February 2007.

  45. Statistical timing for parametric yield prediction of digital integrated circuits.
    J. A. G. Jess, K. Kalafala, S. R. Naidu, R. H. J. M. Otten, and C. Visweswariah.
    IEEE Transactions on Computer-Aided Design of ICs and Systems, volume 25, number 11, pages 2376--2392, November 2006.

  46. First-order incremental block-based statistical timing analysis.
    C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, S. Narayan, D. K. Beece, J. S. Piaget, N. Venkateswaran, and J. G. Hemmett.
    IEEE Transactions on Computer-Aided Design of ICs and Systems, volume 25, number 10, pages 2170--2180, October 2006.

  47. Criticality computation in parameterized statistical timing.
    J. Xiong, V. Zolotov, C. Visweswariah, and N. Venkateswaran.
    Design Automation Conference (DAC), San Francisco, CA, pages 63--68, July 2006.

  48. Criticality computation in parameterized statistical timing.
    J. Xiong, V. Zolotov, C. Visweswariah, and N. Venkateswaran.
    ACM/IEEE international workshop on timing issues in the specification and synthesis of digital systems (TAU), San Jose, CA, pages 119--124, February 2006.

  49. Computation of yield gradients from statistical timing analysis.
    V. Zolotov, J. Xiong, and C. Visweswariah.
    ACM/IEEE international workshop on timing issues in the specification and synthesis of digital systems (TAU), San Jose, CA, pages 125--130, February 2006.

  50. Gate sizing using incremental parameterized statistical timing analysis.
    M. R. Guthaus, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    IEEE International Conference on Computer-Aided Design, San Jose, CA, pages 1029--1036, November 2005.

  51. Parameterized block-based statistical timing analysis with non-Gaussian and nonlinear parameters.
    H. Chang, V. Zolotov, C. Visweswariah, and S. Narayan.
    Design Automation Conference (DAC), Anaheim, CA, pages 71--76, June 2005.

  52. Gate sizing using incremental parameterized statistical timing analysis.
    M. R. Guthaus, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    International Workshop on Logic Synthesis (IWLS), Lake Arrowhead, CA, June 2005.

  53. Parameterized block-based statistical timing analysis with non-Gaussian and nonlinear parameters.
    H. Chang, V. Zolotov, S. Narayan, and C. Visweswariah.
    ACM/IEEE international workshop on timing issues in the specification and synthesis of digital systems (TAU), San Francisco, CA, pages 99--104, February 2005.

  54. Large-scale nonlinear optimization in circuit tuning.
    A. Wächter, C. Visweswariah, and A. R. Conn.
    Future Generation Computer Systems, special issue on the Speedup/PARS workshop in Basel, Germany, Elsevier Science, October 2005, volume 21, number 8, pages 1251--1262.

  55. First-order incremental block-based statistical timing analysis.
    C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, and S. Narayan.
    Design Automation Conference (DAC), San Diego, CA, pages 331--336, June 2004.

  56. First-order parameterized block-based statistical timing analysis.
    C. Visweswariah, K. Ravindran, and K. Kalafala.
    ACM/IEEE international workshop on timing issues in the specification and synthesis of digital systems (TAU), Austin, TX, pages 17--24, February 2004.

  57. Statistical timing for parametric yield prediction of digital integrated circuits.
    J. A. G. Jess, K. Kalafala, S. R. Naidu, R. H. J. M. Otten, and C. Visweswariah.
    Design Automation Conference (DAC), Anaheim, CA, pages 932--937, June 2003.

  58. Exploiting optimality conditions in accurate static circuit tuning.
    C. Visweswariah, A. R. Conn, and L. G. Silva.
    G. Di Pillo and A. Murli, Editors, High performance algorithms and software for nonlinear optimization, Kluwer Academic Publishers, Dordrect, The Netherlands, pages 363--381, 2003.

  59. Time budgeting in a wireplanning context.
    J. Westra, D-J. Jongeneel, R. H. J. M. Otten, and C. Visweswariah.
    Design and Test in Europe (DATE), Messe Munich, Germany, pages 436--441, March 2003.

  60. Uncertainty-aware circuit tuning.
    X. Bai, C. Visweswariah, P. N. Strenski, and D. J. Hathaway.
    Design Automation Conference (DAC), New Orleans, LA, pages 58--63, June 2002.

  61. Noise considerations in circuit optimization.
    C. Visweswariah, R. A. Haring, and A. R. Conn.
    IEEE Transactions on Computer-Aided Design of ICs and Systems, number 6, volume 19, pages 679--690, June 2000.

  62. Two-step algorithms for nonlinear optimization with structured applications.
    A. R. Conn, L. N. Vicente, and C. Visweswariah.
    SIAM Journal on Optimization, volume 9, number 4, pages 924--947, September 1999.

  63. Formulation of static circuit optimization with reduced size, degeneracy and redundancy by timing graph manipulation.
    C. Visweswariah and A. R. Conn.
    IEEE International Conference on Computer-Aided Design, San Jose, CA, pages 244--251, November 1999.

  64. Gradient-based optimization of custom circuits using a static-timing formulation.
    A. R. Conn, I. M. Elfadel, W. W. Molzen, Jr., P. R. O'Brien, P. N. Strenski, C. Visweswariah, and C. B. Whan
    Design Automation Conference (DAC), New Orleans, LA, pages 452--459, June 1999.

  65. Noise considerations in circuit optimization.
    A. R. Conn, R. A. Haring, and C. Visweswariah.
    IEEE International Conference on Computer-Aided Design, San Jose, CA, pages 220--227, November 1998.

  66. JiffyTune: circuit optimization using time-domain sensitivities.
    A. R. Conn, P. K. Coulman, R. A. Haring, G. L. Morrill, C. Visweswariah, and C. W. Wu.
    IEEE Transactions on Computer-Aided Design of ICs and Systems, number 12, volume 17, pages 1292--1309, December 1998.

  67. Circuit optimization via adjoint Lagrangians.
    A. R. Conn, R. A. Haring, C. Visweswariah, and C. W. Wu.
    IEEE International Conference on Computer-Aided Design, San Jose, CA, pages 281--288, November 1997.

  68. Inaccuracies in power estimation during logic synthesis.
    D. Brand and C. Visweswariah.
    IEEE International Conference on Computer-Aided Design, San Jose, CA, pages 388--394, November 1996.

  69. Optimization of custom MOS circuits by transistor sizing.
    A. R. Conn, P. K. Coulman, R. A. Haring, G. L. Morrill, and C. Visweswariah.
    IEEE International Conference on Computer-Aided Design, San Jose, CA, pages 174--180, November 1996.

  70. Incremental event-driven simulation of digital FET circuits.
    C. Visweswariah and J. A. Wehbeh.
    Design Automation Conference (DAC), Dallax, TX, pages 737--741, June 1993.

  71. Stepsize control in piecewise approximate circuit simulation.
    C. Visweswariah.
    Proc. 5th International Conference on VLSI Design, Bangalore, India, pages 287--292, January 1992.

  72. Piecewise approximate circuit simulation.
    C. Visweswariah and R. A. Rohrer.
    IEEE Transactions on Computer-Aided Design of ICs and Systems, vol. CAD-10(7), pages 861--870, July 1991.

  73. M3 - a multi-level, mixed-mode, mixed A/D simulator.
    R. Chadha, C. Visweswariah, and C-F. Chen.
    IEEE Transactions on Computer-Aided Design of ICs and Systems, 11(5):575--585, May 1992.

  74. Efficient simulation of bipolar digital integrated circuits.
    C. Visweswariah and R. A. Rohrer.
    Design Automation Conference (DAC), San Francisco, CA, pages 32--37, June 1991.

  75. Incorporation of inductors in piecewise approximate circuit simulation.
    C. Visweswariah, P. Feldmann, and R. A. Rohrer.
    IEEE International Conference on Computer-Aided Design, Santa Clara, CA, pages 162--165, November 1990.

  76. Piecewise approximate circuit simulation.
    C. Visweswariah and R. A. Rohrer.
    IEEE International Conference on Computer-Aided Design, Santa Clara, CA, pages 248--251, November 1989.

  77. M3 - a multi-level, mixed-mode, mixed A/D simulator.
    R. Chadha, C. Visweswariah, and C-F. Chen.
    IEEE International Conference on Computer-Aided Design, Santa Clara, CA, pages 258--261, November 1988.

  78. Mixed accuracy simulation with SPECS.
    C. Visweswariah and R. A. Rohrer.
    Proc. SRC Techcon, Dallas, TX, pages 284--286, October 1988.

  79. Model development and verification for high level analog blocks.
    C. Visweswariah, R. Chadha, and C-F. Chen.
    Design Automation Conference (DAC), Anaheim, CA, pages 376--382, June 1988.

  80. SPECS2: an integrated circuit timing simulator.
    C. Visweswariah and R. A. Rohrer.
    IEEE International Conference on Computer-Aided Design, Santa Clara, CA, pages 94--97, November 1987.

  81. Simulation of MOS integrated circuits by the waveform relaxation method.
    C. Visweswariah, T. V. Verghese, and S. Mohan.
    Proc. IEEE All-India Students' Symposium on "Recent Trends in CAD," Tiruchirapalli, India, October 1984.

Other publications, including technical reports

  1. Statistical EinsTuner: custom circuit device sizing in the presence of process variation.
    D. K. Beece, J. Xiong, C. Visweswariah, and V. Zolotov.
    IBM Design Automation Workshop (DAW), September 2009.

  2. Timing stack open discussion.
    C. Visweswariah.
    IBM Design Automation Workshop (DAW), September 2009.

  3. Effective waveform for static timing.
    D. D. Ling, S. Abbaspour, P. Feldmann, C. Visweswariah, R. Banerji, and J. Xiong.
    IBM Design Automation Workshop (DAW), Virtual Interactive Presentation (VIP), September 2009.

  4. ASST path selection for process space coverage.
    J. Xiong, V. Zolotov, and C. Visweswariah.
    IBM Design Automation Workshop (DAW), September 2009.

  5. Test margin selection under process variation.
    J. M. Mart&iacutenez, C. Visweswariah, F. Woytowich, and J. Xiong.
    IBM Design Automation Workshop (DAW), September 2009.

  6. Statistical timing: a tool perspective.
    J. Hemmett, V. Zolotov, C. Visweswariah, and N. Venkateswaran.
    IBM Design Automation Workshop (DAW), September 2009.

  7. Single statistical timing run with non-separable process variables.
    V. Zolotov, C. Visweswariah, N. Venkateswaran, J. Hemmett, and J. Xiong.
    IBM Design Automation Workshop (DAW), September 2009.

  8. The value of statistical timing.
    N. C. Buck, E. A. Foreman, P. A. Habitz, J. G. Hemmett, S. G. Shuma, N. Venkateswaran, C. Visweswariah, and X. Wang.
    IBM Design Automation Workshop (DAW), Virtual Interactive Presentation (VIP), September 2009.

  9. Variation-aware at-speed structural test using statistical timing analysis.
    V. Iyengar, S. Venkatesan, J. Xiong, G. Grise, V. Zolotov, D. Lackey, P. Habitz, and C. Visweswariah.
    IBM third conference on Chip Testing Best Practices, March 2007.

  10. Compact modeling of variational waveforms.
    V. Zolotov, J. Xiong, S. Abbaspour, D. J. Hathaway, and C. Visweswariah.
    IBM East Fishkill Technical Exchange Conference, October 2007.

  11. Static timing: back to our roots. (IBM internal only)
    C. Visweswariah and V. Zolotov.
    IBM Design Automation Workshop, East Fishkill, NY, March, 2006.

  12. Criticality computation in parameterized statistical timing. (IBM itnernal only)
    J. Xiong, V. Zolotov, C. Visweswariah, and N. Venkateswaran.
    IBM Design Automation Workshop, East Fishkill, NY, March, 2006.

  13. Efficient modeling of spatial correlations in parameterized statistical timing. (IBM internal only)
    L. Zhang, V. Zolotov, C. Visweswariah, and N. Venkateswaran.
    IBM Design Automation Workshop, East Fishkill, NY, March, 2006.

  14. Computation of yield gradients from statistical timing analysis. (IBM internal only)
    V. Zolotov, J. Xiong, and C. Visweswariah.
    IBM Design Automation Workshop, East Fishkill, NY, March, 2006.

  15. Statistical-based analysis and design for VLSI ASICs and systems-on-chip (SoCs).
    G. W. Doerre and C. Visweswariah.
    EDTS white paper (2nd version), June, 2005.

  16. Statistical timing analysis in support of robust integrated circuit design and optimization.
    D. K. Beece, J. G. Hemmett, K. Kalafala, J. Narasimhan, S. Narayan, J. S. Piaget, N. Venkateswaran, C. Visweswariah, and S. G. Walker.
    IBM Academy Conference on Design for Manufacturability, Somers, NY, May, 2004.

  17. Hierarchical statistical modeling of integrated circuit variability.
    Y. Amemiya and C. Visweswariah.
    IBM Academy Conference on Design for Manufacturability, Somers, NY, May, 2004.

  18. Variability-aware design optimizations using statistical timing.
    M. Guthaus, D. Kung, J. Narasimhan, R. Puri, L. Trevillyan, and C. Visweswariah.
    IBM Academy Conference on Design for Manufacturability, Somers, NY, May, 2004.

  19. Statistical timing and yield prediction of digital integrated circuits.
    S. R. Naidu, C. Visweswariah, J. A. G. Jess, and R. H. J. M. Otten.
    Eindhoven University of Technology, Eindhoven, The Netherlands, Technical report, Department of Electrical Engineering, August 2002.

  20. Ontwerptechnologie 5L050 class notes and teaching materials.
    C. Visweswariah.
    Eindhoven University of Technology, Eindhoven, The Netherlands, Technical report, Department of Electrical Engineering, June 2002.
    Only static timing and sensitivity class notes available in softcopy form.

  21. Computation and chain-ruling of MOSFET sensitivities.
    C. Visweswariah.
    IBM Research Division, T. J. Watson Research Center, Technical Report, February 2002.

  22. White paper on the future of formal static tuning (IBM internal only).
    C. Visweswariah.
    IBM Internal White Paper, January 2000.

  23. Noise considerations in circuit optimization.
    C. Visweswariah, R. A. Haring, and A. R. Conn.
    IBM Research Division, T. J. Watson Research Center, Research Report RC 21505(97014), June 1999.

  24. Two-step algorithms for nonlinear optimization with structured applications.
    A. R. Conn, L. N. Vicente, and C. Visweswariah.
    IBM Research Division, T. J. Watson Research Center, Research Report RC 21198(94689), June 1998.

  25. Electrical and timing simulation.
    C. Visweswariah.
    IBM Research Division, T. J. Watson Research Center, Research Report RC 21191(94676), May 1998.

  26. JiffyTune: circuit optimization using time-domain sensitivities.
    A. R. Conn, P. K. Coulman, R. A. Haring, G. L. Morrill, C. Visweswariah, and C. W. Wu.
    IBM Research Division, T. J. Watson Research Center, Research Report RC 20963(92837), August 1997.

  27. Inaccuracies in gate-level power estimation.
    D. Brand and C. Visweswariah.
    IBM Research Division, T. J. Watson Research Center, Research Report RC 20520, August 1996.

  28. Circuit simulation notes.
    C. Visweswariah.
    Class notes, IBM T. J. Watson Research Center, Yorktown Heights, NY, December 1992.

  29. SPECS users' guide versions 4.06 to 4.23.
    A. McDonald and C. Visweswariah.
    Technical report, IBM Microelectronics, Burlington VT, October 1994.

  30. Variable accuracy circuit simulation with SPECS.
    C. Visweswariah.
    Proc. IBM ITL on Design Automation, Kingston, NY, October 1990.

  31. Incorporation of inductors in piecewise approximate circuit simulation.
    C. Visweswariah, P. Feldmann, and R. A. Rohrer.
    IBM Research Division, T. J. Watson Research Center, Research Report RC 15773, November 1990.

  32. Workshop notes.
    C. Visweswariah, P. Feldmann, A. D. Stein, and X. Zhang.
    SRC-CMU Technology Transfer Course, Carnegie Mellon University, Pittsburgh, PA, August 1989.

  33. Experiments with SPECS at Harris Semiconductor.
    M. Chian and C. Visweswariah.
    Technical report, Harris Semiconductor, Melbourne, FL, March 1989.

  34. Piecewise approximate circuit simulation.
    C. Visweswariah.
    Technical Report CMUCAD-89-28, Carnegie Mellon University, Pittsburgh, PA, May 1989.

  35. Circuit simulation with SPECS.
    C. Visweswariah.
    Technical report, Harris Semiconductor, Melbourne, FL, August 1988.

  36. Data structures for the new MOTIS.
    C. Visweswariah, T. Sheng-Lin, E. Szeto-Lee, R. Chadha, and C-F. Chen.
    Technical report, AT&T Bell Laboratories, Murray Hill, NJ, December 1987.

  37. Conversion of Laplace and Z transforms into state-space representations and its automation.
    K. Singhal, R. Chadha, and C. Visweswariah.
    Technical report, AT&T Bell Laboratories, Murray Hill, NJ, May 1987.

  38. ACME - an analog C model verification tool.
    C. Visweswariah.
    Technical report, AT&T Bell Laboratories, Murray Hill, NJ, January 1987.

  39. SPECS2: a timing simulator.
    C. Visweswariah.
    Technical Report CMUCAD-86-24, Carnegie Mellon University, Pittsburgh, PA, October 1986.

  40. WARMOSS: a time-domain integrated circuit simulator based on waveform relaxation.
    C. Visweswariah.
    Technical report, Indian Institute of Technology, Chennai, India, May 1985.
    Bachelor's thesis.

Publicity

Articles in the press and on the web.

  1. VELCO and partners to create Vermont Weather Analytics Center.
    VELCO press release (picked up by several media sources).
    October 15, 2014.

  2. Locals earn IBM Fellow title.
    C. Wolf.
    Poughkeepsie Journal, April 4, 2013, web and print versions.

  3. IBM Fellows' latest class included Durham IBMer.
    WRAL Tech Wire, April 3, 2013.

  4. IBM names two Fellows from Route 52 plant.
    J. Dinapoli.
    Time Herald-Record, April 4, 2013.

  5. IBM décerne les insignes d'honneur à 8 nouveaux "IBM Fellows".
    Tunisia IT, Le Journal du Net & du Management, April 4, 2013.

  6. IBM awards 8 technical Fellows at its 50th anniversary.
    CIO Magazine, East Africa/Kenya, April 3, 2013.

  7. IBM awards highest technical honor to eight new Fellows as company celebrates 50th anniversary of program.
    Sacramento Bee, April 3, 2013.

  8. IBM Fellows: still ahead of their time, 50 years later.
    G. Tucker.
    A Smarter Planet Blog, April 3, 2013.

  9. US foreign aid efforts get a corporate boost.
    J. Gold.
    MSNBC, June 2, 2011.

  10. Offering advice free of charge.
    S. Ante.
    Wall Street Journal, December 6, 2010.

  11. Engineer honored by IBM.
    Business "What's New?" section, Poughkeepsie Journal, July 21, 2009, on the appointment of Chandu Visweswariah as an IBM Distinguished Engineer.

  12. Statistical timing tool moves from interesting to necessary.
    R. Wilson.
    EDN magazine, June 6, 2008.

  13. Who needs statistical timing and how to use it.
    R. Goering.
    SCD Source "Expert's Corner," November 1, 2007.

  14. Patent claims imperil statistical standards push.
    R. Goering.
    EE Times, June 15, 2007.

  15. Rethinking statistical timing analysis.
    R. Goering.
    EE Times, April 2, 2007.

  16. Chandu Visweswariah: IBM innovation brings statistics to digital-IC design.
    M. Santarini.
    EDN Magazine, May 11, 2006.

  17. Selected for the 12/2005 EE Times "Great Minds, Great Ideas Project" and special issue. Chandu Visweswariah. He's getting the chips to run on time.
    EE Times, Inventor profile, December 5, 2005. Also an essay on innovation.

  18. He's getting the chips to run on time.
    EE Times, November 28, 2005.

  19. Variability upends designers' plans.
    R. Goering.
    EE Times, November 21, 2005.

  20. IBM claims edge on EDA guard in statistical tools.
    R. Goering.
    EE Times, June 6, 2005.

  21. IBM makes EDA play -- offers commercial statistical timing tool.
    M. Santarini.
    EDN Magazine, June 2, 2005.
    Also available at World business news wire.

  22. IBM markets statistical timing analyzer.
    R. Goering.
    EE Times, June 3, 2005.
    Also available at EEProductCenter.com.

  23. IBM opens doors on statistical timing analysis suite.
    Online staff.
    Electronic News, June 3, 2005.

  24. IBM to offer 'statistical timing' solutions for chip designers: Press releases
  25. Statistical analysis moves past 'normal.'
    R. Goering.
    EE Times, March 7, 2005.

  26. Statistical tool shift: it's all in the timing.
    R. Goering.
    EE Times, February 14, 2005.

  27. Designers wary as IBM embraces statistical timing.
    D. Lammers.
    EE Times, February 9, 2004.

  28. IBM uses "EinsStat" statistical analysis timing tool.
    D. Lammers.
    EE Times, February 3, 2004.

  29. Age of 'variability' dawns.
    M. Santarini and N. Mokhoff.
    EE Times, June 9, 2003.

  30. Statistical analysis to yield better chips.
    M. Santarini.
    EE Times, March 28, 2003.

  31. Tau's timing gurus rally for statistical analysis; Researchers: Time to overhaul design.
    R. Goering and R. Wilson.
    EE Times, Issue 1248, December 9, 2002, pages 1, 100, article referencing "Death, Taxes and Failing Chips," invited presentation at TAU 2002.

  32. IBM tool automates resizing of transistors.
    D. Lammers.
    EE Times, Issue 1222, June 10, 2002, pages 51, 60, article on EinsTuner.

  33. IBM gets refined with chip software.
    S. Shankland.
    CNET news.com, May 31, 2002, article about EinsTuner. The same article in Chinese appeared in the Chinese version of CNET, http://www.ccw.com.cn.

  34. Chip Checker: EinsTuner automates the transistor-design process.
    S. Wolpin.
    IBM Think Research, http://www.research.ibm.com/thinkresearch, July 2002.

  35. Automatic circuit tuning.
    IBM Research Magazine, number 1, April 1997, page 8, article about JiffyTune.


Chandu Visweswariah chandu@us.ibm.com

 




Technical Areas