Takashi Ando  Takashi Ando photo       

contact information

Research Staff Member, Master Inventor
Thomas J. Watson Research Center, Yorktown Heights, NY USA


Professional Associations

Professional Associations:  IEEE Electron Devices Society (EDS)  |  The Japan Society of Applied Physics


Takashi Ando received the B.S. and M.E. degrees from the University of Tokyo, Tokyo, Japan, in 1999 and 2001, and the Ph.D. degree from Osaka University, Osaka, Japan, in 2010, all in Materials Science.

Dr. Ando started his career in Fujitsu Limited, Iwate, Japan, in 2001, where he engaged in process integration of Ferroelectric Random Access Memory. He moved to Sony Corporation, Atsugi, Japan, in 2003, and initiated a research on High-k/Metal Gate technology. He pioneered new materials for Gate-Last process and demonstrated the highest carrier mobility for Si channel with appropriate work functions. In addition, he invented a new structure/material for backside illumination CMOS sensor and made a significant contribution to Sony’s imaging device business. He started to work on Gate-First High-k/Metal Gate technology in 2006 when he was assigned to IBM T. J. Watson Research Center. He has been a Research Staff Member since 2008. In his early career in IBM, he developed a novel method of EOT scaling, which was termed ‘remote interfacial layer scavenging’. This technique enabled systematic understanding of EOT scaling and its impacts on carrier mobility, work function control, and reliability. In parallel, he applied the scientific learning to productization of High-k/Metal Gate technology and provided practical solutions to mitigate design/layout dependences of FET characteristics, which enabled successful implementation in 32/22nm SOI products and 32/28nm LP products. For 14nm SOI, he developed FinFET compatible Gate-Last process and Multi-WF offerings at East Fishkill. His recent effort has focused on application of High-k/Metal Gate technology to high mobility channel materials (e.g. SiGe, InGaAs) and BEOL decoupling MIM capacitors. Moreover, he extends his expertise in High-k materials to emerging new fields, such as Neuromorphic Computing hardware.

He received three IBM Outstanding Technical Achievement Awards and one IBM Research Division Award for his contribution to High-k/Metal Gate Technology and SiGe FinFET Technology. He contributed to IBM Research Extraordinary Accomplishment (the highest honor in IBM Research) 'High-k/metal-gate Technology for High Performance Server and Low Power Mobile Applications' in 2016. He was appointed to IBM Master Inventor in 2016. He has authored or co-authored more than 100 publications in peer-reviewed journals, refereed conference proceedings, and book chapters. He is a recipient of the Japan Society of Applied Physics Young Scientist Award in 2011 and IEEE EDS George E. Smith Award in 2013. He has served technical program committees for JSAP Gate Stack conference (2006-2008), SISC (2013-2015), INFOS (2012-present), and IEDM (2017-present).