Augusto Vega is a Research Staff Member within the Reliability and Power-Aware Microarchitecture department at IBM T. J. Watson Research Center. He has been involved in research and development work in support of IBM System p and Data Centric Systems. His primary focus area is power-aware computer architectures and associated system solutions. He has developed techniques to reduce chip power consumption in multicore/manycore chips for multi-threaded applications, exploiting core folding, frequency/voltage scaling and low-power ("sleep") modes. His research interests are in the areas of high performance, power/reliability-aware computer architectures, distributed and parallel computing, and performance analysis tools and techniques.
In July 2013, he received a Ph.D. degree on Computer Architecture from Polytechnic University of Catalonia (UPC), Spain. Previously, he received a M.Sc. degree on Computer Architecture, Networks and Systems in 2009 from Polytechnic University of Catalonia (UPC), Spain.